SNVSAR5B December   2016  – March 2018 LMR23625-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Load, VIN = 12 V, PFM Option
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency Peak-Current-Mode Control
      2. 8.3.2  Adjustable Output Voltage
      3. 8.3.3  EN/SYNC
      4. 8.3.4  VCC, UVLO
      5. 8.3.5  Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions
      6. 8.3.6  Power Good (PGOOD)
      7. 8.3.7  Internal Compensation and CFF
      8. 8.3.8  Bootstrap Voltage (BOOT)
      9. 8.3.9  Overcurrent and Short-Circuit Protection
      10. 8.3.10 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 CCM Mode
      4. 8.4.4 Light Load Operation (PFM Option)
      5. 8.4.5 Light Load Operation (FPWM Option)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Output Voltage Setpoint
        3. 9.2.2.3  Switching Frequency
        4. 9.2.2.4  Inductor Selection
        5. 9.2.2.5  Output Capacitor Selection
        6. 9.2.2.6  Feed-Forward Capacitor
        7. 9.2.2.7  Input Capacitor Selection
        8. 9.2.2.8  Bootstrap Capacitor Selection
        9. 9.2.2.9  VCC Capacitor Selection
        10. 9.2.2.10 Undervoltage Lockout Setpoint
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact Layout for EMI Reduction
      2. 11.1.2 Ground Plane and Thermal Considerations
      3. 11.1.3 Feedback Resistors
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRR|12
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DDA Package
8-Pin SOIC
Top View
LMR23625-Q1 lmr23625-q1-pinout-soic-8-top-view-snvsar5.gif
DRR Package
12-Pin WSON with PGOOD
Top View
LMR23625-Q1 lmr23625-q1-pinout-wson-12-pgood-top-view-snvsar5.gif

Pin Functions

PINI/O (1)DESCRIPTION
NAMESOICWSON with PGOOD
SW 1 1, 2 P Switching output of the regulator. Internally connected to both power MOSFETs. Connect to power inductor.
BOOT 2 3 P Bootstrap capacitor connection for high-side driver. Connect a high-quality 470-nF capacitor from BOOT to SW.
VCC 3 4 P Internal bias supply output for bypassing. Connect a 2.2-μF, 16-V or higher capacitance bypass capacitor from this pin to AGND. Do not connect external loading to this pin. Never short this pin to ground during operation.
FB 4 5 A Feedback input to regulator, connect the feedback resistor divider tap to this pin.
PGOOD N/A 6 A Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other DC voltage no higher than 12 V.
EN/SYNC 5 8 A Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float. Adjust the input undervoltage lockout with two resistors. The internal oscillator can be synchronized to an external clock by coupling a positive pulse into this pin through a small coupling capacitor. See EN/SYNC for detail.
AGND 6 7 G Analog ground pin. Ground reference for internal references and logic. Connect to system ground.
VIN 7 9, 10 P Input supply voltage.
PGND 8 12 G Power ground pin, connected internally to the low side power FET. Connect to system ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible.
PAD 9 13 G Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path of the die. Must be used for heat sinking to ground plane on PCB.
NC N/A 11 N/A Not for use. Leave this pin floating.
(1) A = Analog, P = Power, G = Ground.