SNVSAH3E February   2018  – July 2020 LMR23625

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency Peak-Current-Mode Control
      2. 7.3.2 Adjustable Output Voltage
      3. 7.3.3 Enable/Sync
      4. 7.3.4 VCC, UVLO
      5. 7.3.5 Minimum ON-time, Minimum OFF-time and Frequency Foldback at Drop-out Conditions
      6. 7.3.6 Internal Compensation and CFF
      7. 7.3.7 Bootstrap Voltage (BOOT)
      8. 7.3.8 Overcurrent and Short-Circuit Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation (PFM Option)
      5. 7.4.5 Light Load Operation (FPWM Option)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  Feed-forward Capacitor
        7. 8.2.2.7  Input Capacitor Selection
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  VCC Capacitor Selection
        10. 8.2.2.10 Undervoltage Lockout Set-Point
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Compact Layout for EMI Reduction
    4. 10.4 Ground Plane and Thermal Considerations
    5. 10.5 Feedback Resistors
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDA|8
  • DRR|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.5 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for voltage drops along the traces and provide the best output accuracy. Route the voltage sense trace from the load to the feedback resistor divider away from the SW node path and the inductor to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high-value resistors are used to set the output voltage. TI recommends routing the voltage sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further shielding for the voltage feedback path from EMI noises.