SNVSAH2 Data sheet

SNVSAH2E December 2015 – August 2020 LMR23630

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DDA|8
DRR|12

Thermal pad, mechanical data (Package|Pins)

DDA|8
- PPTD058I
DRR|12
- PPTD338C

Orderable Information

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25 °C, and are provided for reference purposes only.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY (VIN PIN)
V_IN	Operation input voltage		4		36	V
VIN_UVLO	Undervoltage lockout thresholds	Rising threshold	3.3	3.7	3.9	V
		Falling threshold	2.9	3.3	3.5	V
I_SHDN	Shutdown supply current	Falling threshold		2	4	μA
I_SHDN	Shutdown supply current	V_EN = 0 V, V_IN = 12 V, T_J = –40°C to 125°C		2	4	μA
I_Q	Operating quiescent current (non- switching)	V_IN =12 V, V_FB = 1.1 V, T_J = –40°C to 125°C, PFM mode		75		μA
ENABLE (EN/SYNC PIN)
V_{EN_H}	Enable rising threshold voltage		1.4	1.55	1.7	V
V_{EN_HYS}	Enable hysteresis voltage			0.4		V
V_WAKE	Wake-up threshold		0.4			V
I_EN	Input leakage current at EN pin	V_IN = 4 V to 36 V, V_EN= 2 V		10	100	nA
		V_IN = 4 V to 36 V, V_EN= 2 V		10	100	nA
		V_IN = 4 V to 36 V, V_EN= 36 V			1	μA
		V_IN = 4 V to 36 V, V_EN= 36 V			1	μA
VOLTAGE REFERENCE (FB PIN)
V_REF	Reference voltage	V_IN = 4.0 V to 36 V, T_J = 25 °C	0.985	1	1.015	V
V_REF	Reference voltage	V_IN = 4.0 V to 36 V, T_J = –40°C to 125°C	0.98	1	1.02	V
I_{LKG_FB}	Input leakage current at FB pin	V_FB= 1 V		10		nA
POWER GOOD (PGOOD PIN)
V_{PG_OV}	Power-good flag overvoltage tripping threshold	% of reference voltage	104%	107%	110%
V_{PG_UV}	Power-good flag undervoltage tripping threshold	% of reference voltage	92%	94%	96.5%
V_{PG_HY}_S	Power-good flag recovery hysteresis	% of reference voltage		1.5%
V_{IN_PG_MIN}	Minimum V_IN for valid PGOOD output	50 μA pullup to PGOOD pin, V_EN = 0 V, T_J = 25°C			1.5	V
V_{PG_LOW}	PGOOD low level output voltage	50 μA pullup to PGOOD pin, V_IN = 1.5 V, V_EN = 0 V			0.4	V
V_{PG_LOW}	PGOOD low level output voltage	0.5 mA pullup to PGOOD pin, V_IN = 13.5 V, V_EN = 0 V			0.4	V
INTERNAL LDO (VCC PIN)
V_CC	Internal LDO output voltage			4.1		V
VCC_UVLO	VCC undervoltage lockout thresholds	Rising threshold	2.8	3.2	3.6	V
VCC_UVLO	VCC undervoltage lockout thresholds	Falling threshold	2.4	2.8	3.2	V
CURRENT LIMIT
I_{HS_LIMIT}	Peak inductor current limit	HSOIC package	3.8	5	6.2	A
I_{HS_LIMIT}	Peak inductor current limit	WSON package	4	5.5	6.6	A
I_{LS_LIMIT}	Valley inductor current limit	HSOIC package	2.9	3.6	4.6	A
I_{LS_LIMIT}	Valley inductor current limit	WSON package	2.9	3.6	4.2	A
I_{L_ZC}	Zero cross current limit	HSOIC and WSON package		–0.04		A
I_{L_NEG}	Negative current limit (FPWM option)	SOIC and WSON package	–2.7	–2	–1.3	A
INTEGRATED MOSFETS
R_{DS_ON_HS}	High-side MOSFET ON-resistance	SOIC package, V_IN = 12 V, I_OUT = 1 A		185		mΩ
R_{DS_ON_HS}	High-side MOSFET ON-resistance	WSON package, V_IN = 12 V, I_OUT = 1 A		160		mΩ
R_{DS_ON_LS}	Low-side MOSFET ON-resistance	SOIC package, V_IN = 12 V, I_OUT = 1 A		105		mΩ
R_{DS_ON_LS}	Low-side MOSFET ON-resistance	WSON package, V_IN = 12 V, I_OUT = 1 A		95		mΩ
THERMAL SHUTDOWN
T_SHDN	Thermal shutdown threshold		162	170	178	°C
T_HYS	Hysteresis			15		°C