The power-good flag function (PG output pin) of the LMR38015-Q1 can be used as a flag to alert the host microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions such as a current limiting condition causing the output to fall out of regulation or a thermal shutdown event. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions lasting less than t_PG do not trip the power-good flag. Note that during soft-start events power-good is held low and is released upon the output voltage reaching the final regulated value.

The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic supply. The power-good output can also be pulled up to either VCC or V_OUT, through a 100-kΩ resistor, as desired. If this function is not needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low. With EN low, power good remains in the valid state as long as the input voltage is greater than or equal to 2 V (typical). Note that in the event EN goes back high, Power-Good only goes high after the output voltage reaches the final value. TI recommends to limit the current into the power-good flag pin to less than 5-mA D.C. The maximum current is internally limited to approximately 35 mA when the device is enabled and approximately 65 mA when the device is disabled. The internal current limit protects the device from any transient currents that can occur when discharging a filter capacitor connected to this output.

Figure 7-5 Static Power-Good Operation

Figure 7-6 Power-Good Timing Behavior