SNVSCH7 February   2024 LMR38025

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Peak Current Mode Control
      2. 7.3.2  Adjustable Output Voltage
      3. 7.3.3  Enable
      4. 7.3.4  Switching Frequency and Synchronization (RT/SYNC)
      5. 7.3.5  Power-Good Flag Output
      6. 7.3.6  Minimum On Time, Minimum Off Time, and Frequency Foldback
      7. 7.3.7  Bootstrap Voltage
      8. 7.3.8  Overcurrent and Short-Circuit Protection
      9. 7.3.9  Soft Start
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto Mode
      2. 7.4.2 Forced PWM Operation
      3. 7.4.3 Dropout
      4. 7.4.4 Minimum Switch On Time
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Choosing the Switching Frequency
        3. 8.2.2.3 FB for Adjustable Output
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 CBOOT
        8. 8.2.2.8 External UVLO
        9. 8.2.2.9 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 Switching Frequency and Synchronization (RT/SYNC)

The switching frequency of the LMR38025 can be programmed by the resistor RT from the RT/SYNC pin and GND pin. The RT/SYNC pin cannot be left floating or shorted to ground. To determine the timing resistance for a given switching frequency, use Equation 2 or the curve in Figure 7-3. Table 7-1 gives typical RT values for a given fSW.

Equation 2. R T ( k 𝛀 ) = 30970 × f SW ( k Hz ) – 1 . 027
GUID-20230510-SS0I-X765-G5KW-CZ8W8VPSFCJX-low.svg Figure 7-3 RT Versus Frequency Curve
Table 7-1 Typical Frequency Setting RT Resistance
fSW (kHz)RT (kΩ)
200133
40064.9
50052.3
75034.8
100025.5
150016.9
200012.7
220011.5

The LMR38025 switching action can also be synchronized to an external clock from 300kHz to 2.1MHz. Connect a square wave to the RT/SYNC pin through either circuit network shown in Figure 7-4. The internal oscillator is synchronized by the falling edge of external clock. The recommendations for the external clock include: high level no lower than 2.0V, low level no higher than 0.6V, and must have a logic high pulse-width greater than 50ns. When using a low impedance signal source, the frequency setting resistor RT is connected in parallel with an AC coupling capacitor, CCOUP, to a termination resistor, RTERM (for example, 50Ω). The two resistors in series provide the default frequency setting resistance when the signal source is turned off. Use a 1pF ceramic capacitor for CCOUP.

GUID-20230509-SS0I-GSK7-3LH0-XDQNJK6SWH7J-low.svg Figure 7-4 Synchronizing to an External Clock