SLUSEG8D October   2021  – April 2024 LMR54406 , LMR54410

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 System Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed Frequency Peak Current Mode Control
      2. 7.3.2 Adjustable Output Voltage
      3. 7.3.3 Enable
      4. 7.3.4 Minimum ON Time, Minimum OFF Time, and Frequency Foldback
      5. 7.3.5 Bootstrap Voltage
      6. 7.3.6 Overcurrent and Short Circuit Protection
      7. 7.3.7 Soft Start
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation (PFM Version)
      5. 7.4.5 Light-Load Operation (FPWM Version)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Set-Point
        2. 8.2.2.2 Switching Frequency
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Bootstrap Capacitor
        7. 8.2.2.7 Undervoltage Lockout Set-Point
        8. 8.2.2.8 Replacing Non Sync Converter
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Compact Layout for EMI Reduction
        2. 8.4.1.2 Feedback Resistors
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.4 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters. Minimizing the output capacitance to keep cost and size down is generally desired. The output capacitor or capacitors, COUT, must be chosen with care because it directly affects the steady state output voltage ripple, loop stability, and output voltage overshoot and undershoot during load current transient. The output voltage ripple is essentially composed of two parts. One part is caused by the inductor ripple current flowing through the Equivalent Series Resistance (ESR) of the output capacitors:

Equation 10. GUID-07910EAE-76C0-42FB-9397-1277259FA904-low.gif

The other part is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 11. GUID-161A1414-FC54-4DED-8380-D0DDB9E80A74-low.gif

The two components of the voltage ripple are not in-phase, therefore, the actual peak-to-peak ripple is less than the sum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rates. When a large load step occurs, output capacitors provide the required charge before the inductor current can slew to an appropriate level. The control loop of the converter usually requires eight or more clock cycles to regulate the inductor current equal to the new load level during this time. The output capacitance must be large enough to supply the current difference for eight clock cycles to maintain the output voltage within the specified range. Equation 12 shows the minimum output capacitance needed for a specified VOUT overshoot and undershoot.

Equation 12. GUID-AA06A704-EDF1-4B99-B1EC-F10699E5D8EF-low.gif

where

  • KIND = Ripple ratio of the inductor current (ΔiL / IOUT)
  • IOL = Low level output current during load transient
  • IOH = High level output current during load transient
  • VOUT_SHOOT = Target output voltage overshoot or undershoot

For this design example, the target output ripple is 30 mV. Assuming ΔVOUT_ESR = ΔVOUT_C = 30 mV, choose KIND = 0.4. Equation 10 yields ESR no larger than 75 mΩ and Equation 11 yields COUT no smaller than 2.38 µF. For the target overshoot and undershoot limitation of this design, ΔVOUT_SHOOT = 8% × VOUT = 400 mV. The COUT can be calculated to be no less than 14.3 µF by Equation 12. In summary, the most stringent criteria for the output capacitor is 14.3 µF. Considering derating, one 22-µF, 16-V, X7R ceramic capacitor with 10-mΩ ESR is used.