SNAS879 December   2024 LMR60420

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Undervoltage Lockout (UVLO)
      2. 7.3.2 Soft Start and Recovery from Dropout
      3. 7.3.3 Frequency Selection With RT
      4. 7.3.4 MODE/SYNC Pin Control
      5. 7.3.5 Output Voltage Selection
      6. 7.3.6 Current Limit
      7. 7.3.7 Hiccup Mode
      8. 7.3.8 Power-Good Function
      9. 7.3.9 Spread Spectrum
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Continuous Conduction Mode (CCM)
        2. 7.4.2.2 Auto Mode - Light Load Operation
        3. 7.4.2.3 FPWM Operation - Light Load Operation
        4. 7.4.2.4 Minimum On-Time
        5. 7.4.2.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency Selection
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor (CBOOT) Selection
        6. 8.2.2.6 FB Voltage Divider for Adjustable Output Voltages
          1. 8.2.2.6.1 Feedforward Capacitor (CFF) Selection
        7. 8.2.2.7 RPG - PG Pullup Resistor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Plane Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5 V, VEN = 5V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY (VIN PIN)
VINUVLO(R) VIN UVLO rising threshold VIN rising (needed to start up) 2.7 3.0 3.2 V
VINUVLO(F) VIN UVLO falling threshold VIN falling (once operating) 2.65 V
VINUVLO(H) VIN UVLO hysteresis 0.6 V
VINOVP(R) VIN OVP rising threshold VIN rising needed to switch device into PFM operation 35 37 39 V
VINOVP(F) VIN OVP falling threshold VIN falling needed to switch device from PFM to FPWM operation 34 36 38 V
VINOVP(H) VIN OVP hysteresis 0.6 0.95 1.2 V
IQ(FIX-3.3V) Total VIN quiescent current, fixed 3.3V output, no switching  VIN = 13.5V, IOUT = 0A, VFB = 3.3V + 4%, TJ = 25℃, Auto mode enabled  3.55 5 µA
IQ(ADJ-3.3V) Total VIN quiescent current, adjustable 3.3V output, no switching VIN = 13.5V, IOUT = 0A, VFB = 1V + 4%, Auto mode enabled  3.55 5 µA
IQ-SD VIN shutdown supply current VEN = 0V, +25c degrees results only 0.65 1 µA
ENABLE (EN PIN)
VEN-TH(R) Enable voltage rising threshold VEN rising 1.15 1.25 1.35 V
VEN-TH(F) Enable input low threshold VEN falling 0.9 1 1.1 V
VEN-HYS Enable voltage hysteresis 275 mV
IEN-LKG Enable input leakage current VEN = VIN 1 665 nA
VOLTAGE REFERENCE (FB PIN)
VFB Internal feedback reference voltage FPWM mode 0.99 1.0 1.01 V
IFB-LKG Feedback pin input leakage current VFB = 1V, adjustable output voltage 0.09 50 nA
VOUT(3.3V) 3.3V fixed output voltage FPWM mode, FB pin short to VOUT  3.24 3.3 3.35 V
VOUT(5V) 5.0V fixed output voltage FPWM mode, FB short to VOUT  4.9 5 5.075 V
START-UP
tSS Internal fixed soft start time Time from first SW pulse to VREF at 90% of set point 6 ms
CURRENT LIMITS AND HICCUP
IHS-LIM High side peak current limit Duty-cycle approaches 0% 2.96 3.6 4.4 A
ILS-LIM Low side valley current limit Valley current limit on LS FET 2.0 2.5 3.0 A
ILS-NEG-LIM Low side negative current limit Sinking current limit on LS FET, FPWM Mode –1.2 –0.85 –0.6 A
IL-ZC-LIM Zero-cross current limit VVCC = 3.3V, Auto mode 40 mA
VHIC Over-current hiccup threshold on FB Pin LS FET on-time > 165 ns, not during soft start 0.14 0.2 0.25 V
POWER GOOD (PG PIN)
VPG-OVP(R) PG overvoltage rising threshold % of FB voltage (Adj) 105 107 109.7 %
VPG-OVP(F) PG overvoltage falling threshold % of FB voltage (Adj) 104 106 108 %
VPG-UVP(R) PG undervoltage rising threshold % of FB voltage (Adj) 92 94 96.6 %
VPG-UVP(F) PG undervoltage falling threshold % of FB voltage (Adj)  91 93 95 %
tPG-DEGLITCH(F) Deglitch filter delay on PG falling edge 42 52 81 µs
tPG-DEGLITCH(R) Deglitch filter delay on PG rising edge 1.0 2.0 3.0 ms
VIN(PG-VALID) Minimum VIN for valid PG output VOL(PG) < 0.4V, RPU =  10kΩ, VPU = 5V 1.25 V
RON(PG) PG ON resistance IPG = 1mA 165 420 Ω
SWITCHING FREQUENCY (RT PIN)
fSW1(FPWM) Switching frequency, FPWM operation RRT = 16.7kΩ, 1% 1800 2000 2200 kHz
fSW2(FPWM) Switching frequency, FPWM operation RRT = 34.4kΩ, 1% 900 1000 1100 kHz
SYNCHRONIZATION (MODE/SYNC PIN)
VIH to enter FPWM Sync pin voltage to enter FPWM 0.5 0.85 V
VIL to exit FPWM Sync pin voltage to exit FPWM 0.35 0.7 V
VIH(MODE/SYNC) MODE/SYNC input high level threshold 1.3 V
VIL(MODE/SYNC) MODE/SYNC input low level threshold 0.35 V
tCLKIN(TON) Minimum positive pulse width of external sync signal 150 ns
TCLKIN(TOFF) Minimum negative pulse width of external sync signal 150 ns
POWER STAGE
RDS-ON-HS High-side FET ON resistance ISW = 500mA, VBOOT-SW = 3.8V 120 240 mΩ
RDS-ON-LS Low-side FET ON resistance ISW = 500mA, VBOOT-SW = 3.8V 80 160 mΩ
tON-MIN(1)
Minimum on-time

 30 ns
tOFF-MIN(1) Minimum off-time 89 ns
THERMAL SHUTDOWN
TSD Thermal Shutdown(1) Shutdown threshold 155 165 176 ºC
Recovery threshold 156 ºC
(1) Not tested in production.