The PCB layout of any DC/DC converter
is critical to the optimal performance of the design. Poor PCB layout can disrupt
the operation of an otherwise good schematic design. Even if the converter regulates
correctly, bad PCB layout can mean the difference between a robust design and one
that cannot be mass produced. Furthermore, to a great extent, the EMI performance of
the regulator is dependent on the PCB layout. In a buck converter, the most critical
PCB feature is the loop formed by the input capacitor or capacitors and power
ground, as shown in Figure 8-26. This loop carries large transient currents that can cause large transient
voltages when reacting with the trace inductance. These unwanted transient voltages
disrupt the proper operation of the converter. Because of this, the traces in this
loop must be wide and short, and the loop area as small as possible to reduce the
parasitic inductance. Figure 8-27 shows a recommended layout for the critical components of the LMR664x0-Q1.
- Place the input capacitors as
close as possible to the VIN and GND terminals.
- Place bypass capacitor for VCC
close to the VCC pin. This capacitor must be placed close to the device
and routed with short, wide traces to the VCC and GND pins.
- If an external
CBOOT capacitor is desired: Place CBOOT close
to the device with short/wide traces to the BOOT and SW pins.
- Place the feedback divider as
close as possible to the VOUT / FB pin of the device. Place
RFBB, RFBT, and CFF, if used, physically
close to the device. The connections to VOUT / FB and GND must be
short and close to those pins on the device. The connection to VOUT
can be somewhat longer. However, the latter trace must not be routed near any
noise source (such as the SW node) that can capacitively couple into the
feedback path of the regulator.
- Use at least one ground plane
in one of the middle layers. This plane acts as a noise shield and as a
heat dissipation path.
- Provide wide paths for VIN,
VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes
efficiency.
- Provide enough PCB area for
proper heat-sinking. As stated in Section 8.2.1.2.10, enough copper area must be used to make sure of low RθJA,
commensurate with the maximum load current and ambient temperature. The top and
bottom PCB layers must be made with two-ounce copper and no less than one ounce.
If the PCB design uses multiple copper layers (recommended), these thermal vias
can also be connected to the inner layer heat-spreading ground planes.
- Keep switch area small.
Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time, the total area of this node must be minimized to
help reduce radiated EMI.
See the following PCB layout
resources for additional important guidelines: