SNVSCJ2 December   2023 LMR66410-Q1 , LMR66420-Q1 , LMR66430-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Start-Up, and Shutdown
      2. 7.3.2  External CLK SYNC (With MODE/SYNC)
        1. 7.3.2.1 Pulse-Dependent MODE/SYNC Pin Control
      3. 7.3.3  Power-Good Output Operation
      4. 7.3.4  Internal LDO, VCC, and VOUT/FB Input
      5. 7.3.5  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      6. 7.3.6  Output Voltage Selection
      7. 7.3.7  Spread Spectrum
      8. 7.3.8  Soft Start and Recovery from Dropout
        1. 7.3.8.1 Recovery from Dropout
      9. 7.3.9  Current Limit and Short Circuit
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 Auto Mode – Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode – Light Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1 - Automotive Synchronous Buck Regulator at 2.2 MHz
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Choosing the Switching Frequency
          2. 8.2.1.2.2  Setting the Output Voltage
            1. 8.2.1.2.2.1 VOUT / FB for Adjustable Output
          3. 8.2.1.2.3  Inductor Selection
          4. 8.2.1.2.4  Output Capacitor Selection
          5. 8.2.1.2.5  Input Capacitor Selection
          6. 8.2.1.2.6  CBOOT
          7. 8.2.1.2.7  VCC
          8. 8.2.1.2.8  CFF Selection
          9. 8.2.1.2.9  External UVLO
          10. 8.2.1.2.10 Maximum Ambient Temperature
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 - Automotive Synchronous Buck Regulator at 400 kHz
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V, VOUT = 3.3 V. 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VINMIN Input voltage rising threshold for start-up Before start-up 3.2 3.35 3.5 V
Input voltage falling threshold Once operating 2.45 2.7 3 V
ISD(VIN) Shutdown quiescent current at VIN pin EN = 0 V 0.25 1 µA
IBIAS Non-switching input current at VOUT/FB Fixed 5.0-V Vout, VVOUT/FB = 5.25 V 4.2 6.5 µA
IBIAS Non-switching input current at VOUT/FB Fixed 3.3-Vout, VVOUT/FB = 3.47 V 4.2 6.5 µA
IQVIN(nonsw) Non-switching input current; measured at VIN pin (1) Fixed 5-V VOUT, VVOUT/FB = 5.25 V 1.6 3 µA
IQVIN(nonsw) Non-switching input current; measured at VIN pin (1) Fixed 3.3-V VOUT, VVOUT/FB = 3.47 V 1.2 2.2 µA
ENABLE (EN PIN)
VEN-WAKE EN wakeup threshold 0.5 0.7 1 V
VEN-VOUT Precision enable rising threshold for VOUT 1.16 1.23 1.3 V
VEN-HYST Enable hysteresis below VEN-VOUT 0.3 0.35 0.4 V
ILKG-EN Enable pin input leakage current VEN = VIN = 13.5 V 10 nA
INTERNAL LDO (VCC PIN)
VCC VCC pin output voltage VFB = 0 V, IVCC = 1 mA 3.1 3.3 3.45 V
VOLTAGE FEEDBACK (VOUT/FB PIN)
VOUT Output voltage accuracy for fixed VOUT 3.3-V VOUT, VIN = 3.6 V to 36 V, FPWM Mode 3.27 3.3 3.32 V
5-V VOUT, VIN = 5.5 V to 36 V, FPWM Mode 4.94 5.00 5.06 V
VFB Internal reference voltage accuracy VOUT = 1 V, VIN = 3.0 V to 36 V, FPWM Mode 0.99 1.00 1.01 V
IFB(LKG) FB input current Adjustable configuration, FB = 1 V 10 nA
CURRENT LIMITS
IPEAKMAX High-side peak current limit LMR66430-Q1 3.9 4.4 5 A
IVALMAX Low-side valley current limit LMR66430-Q1 2.9 3.5 4 A
IPEAKMIN Minimum peak current limit LMR66430-Q1, Auto Mode 0.55 0.69 0.86 A
INEGMIN Low-side valley current negative limit LMR66430-Q1, FPWM Mode -1.5 -1.3 -1 A
IPEAKMAX High-side peak current limit LMR66420-Q1 2.8 3.4 3.9 A
IVALMAX Low-side valley current limit  LMR66420-Q1 1.9 2.2 2.53 A
IPEAKMIN Minimum peak current limit  LMR66420-Q1, Auto Mode 0.37 0.5 0.65 A
INEGMIN Negative current limit  LMR66420-Q1, FPWM Mode -1 -0.8 -0.6 A
IPEAKMAX High-side peak current limit LMR66410-Q1 1.4 1.8 2.1 A
IVALMAX Low-side valley current limit LMR66410-Q1 0.9 1.1 1.4 A
IPEAKMIN Minimum peak current limit LMR66410-Q1, Auto Mode 0.17 0.27 0.35 A
INEGMIN Low-side valley current negative limit LMR66410-Q1, FPWM Mode -1 -0.8 -0.6 A
IZC Zero-cross current limit Auto Mode 30 80 135 mA
POWER GOOD (PG PIN)
PGOV PG upper threshold - rising % of VOUT/FB (Fixed or Adj. output) 104 108 111 %
PGUV PG upper threshold - falling % of VOUT/FB (Fixed or Adj. output) 89 91 94.2 %
PGHYST PG recovery hysteresis for OV % of VOUT/FB target regulation voltage 2 2.4 2.8 %
PG recovery hysteresis for UV % of VOUT/FB target regulation voltage 2 3.3 4.6 %
VPG-VAL Minimum VIN for PG function VEN = 0 V, RPG_PU = 10 kΩ 1.5 V
RPG PG ON resistance VEN = 3.3 V, 200-µA pullup current 100 Ω
RPG PG ON resistance VEN = 0 V, 200-µA pullup current 100 Ω
tRESET_FILTER PG deglitch delay at falling edge 25 40 75 µs
tPG_ACT Delay time to PG high signal 1.35 2.5 4 ms
SOFT START
tSS Time from first SW pulse to VOUT/FB at 90% of set point 2 3.5 4.6 ms
tHICCUP Time in hiccup before retry soft start 30 50 75 ms
OSCILLATOR (SYNC/MODE PIN)
tPULSE_H High duration needed to be recognized as a pulse 100 ns
tPULSE_L​​​ Low duration needed to be recognized as a pulse 100 ns
tSYNC High/Low level pulse maximum duration to be recognized as a valid clock signal 6 µs
tMODE Time at one level needed to indicate FPWM or Auto Mode 12.5 µs
FSW(2.2MHz) Switching Frequency with fixed 2.2 MHz 2100 2200 2300 kHz
fSYNC Frequency SYNC range 0.2 2.5 MHz
VMODE_L SYNC/MODE input voltage low level threshold 1 V
VMODE_H SYNC/MODE input voltage high level threshold 1.6 V
SWITCH NODE
tON-MIN Minimum HS switch on-time FPWM mode IOUT = 1 A, 2.2 MHz fixed 65 75 ns
tOFF-MIN Minimum HS switch off-time 60 85 ns
tON-MAX Maximum HS switch on-time HS timeout in dropout 6 9 13 µs
POWER STAGE
VBOOT_UVLO Voltage on BOOT pin compared to SW which will turnoff high-side switch 2.1 V
RDSON-HS High-side MOSFET on-resistance Load = 1 A 132 260 mΩ
RDSON-LS Low-side MOSFET on-resistance Load = 1 A 75 140 mΩ
(1) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.