SNVSCJ3 December   2023 LMR66410 , LMR66420 , LMR66430

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Start-Up, and Shutdown
      2. 7.3.2  External CLK SYNC (With MODE/SYNC)
        1. 7.3.2.1 Pulse-Dependent MODE/SYNC Pin Control
      3. 7.3.3  Adjustable Switching Frequency (with RT)
      4. 7.3.4  Power-Good Output Operation
      5. 7.3.5  Internal LDO, VCC, and VOUT/FB Input
      6. 7.3.6  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      7. 7.3.7  Output Voltage Selection
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Soft Start and Recovery from Dropout
        1. 7.3.9.1 Recovery from Dropout
      10. 7.3.10 Current Limit and Short Circuit
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 Auto Mode – Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode – Light Load Operation
        4. 7.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Synchronous Buck Regulator at 400 kHz
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1  Choosing the Switching Frequency
        2. 8.2.3.2  Setting the Output Voltage
          1. 8.2.3.2.1 VOUT / FB for Adjustable Output
        3. 8.2.3.3  Inductor Selection
        4. 8.2.3.4  Output Capacitor Selection
        5. 8.2.3.5  Input Capacitor Selection
        6. 8.2.3.6  CBOOT
        7. 8.2.3.7  VCC
        8. 8.2.3.8  CFF Selection
        9. 8.2.3.9  External UVLO
        10. 8.2.3.10 Maximum Ambient Temperature
      4. 8.2.4 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by production testing.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IQVIN Input current to VIN VIN = 13.5 V, Fixed 3.3-V VOUT, IOUT = 0 A, Auto mode 1.5 µA
VIN = 13.5 V, Fixed 5-V VOUT, IOUT = 0 A, Auto mode 2 µA
POWER STAGE
VDROP1 Input to output voltage differential to maintain VOUT regulation ≥ 95%, with frequency foldback VOUT = 3.3-V, fixed 2.2 MHz, IOUT = 1 A 0.2 V
VOUT = 5-V, fixed 2.2 MHz, IOUT = 1 A 0.2 V
VDROP2 Input to output voltage differential to maintain VOUT regulation ≥ 95% and FSW ≥1.85 MHz VOUT = 3.3-V, fixed 2.2 MHz, IOUT = 1 A 0.7 V
Input to output voltage differential to maintain VOUT regulation ≥ 95% and FSW ≥ 1.85 MHz VOUT = 5-V, fixed 2.2 MHz trim, IOUT = 1 A 0.9 V
DMAX Maximum switch duty cycle While in frequency fold-back 98 %
FSW = 1.85 MHz, VOUT = 5.0-V, IOUT = 1 A 87 %
RFBPARA(min) Minimum value of parallel FB resistor : RFBT parallel RFBB 5 KΩ
PROTECTION
TSD(trip) Thermal shutdown threshold Temperature rising 158 168 186 °C
TSD(hyst) Thermal shutdown hysteresis 15 20 °C