SNIS167E March   2013  – October 2017 LMT84

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Tables
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Accuracy Characteristics
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 LMT84 Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mounting and Thermal Conductivity
      2. 8.4.2 Output Noise Considerations
      3. 8.4.3 Capacitive Loads
      4. 8.4.4 Output Voltage Shift
  9. 9 Application and Implementation
    1. 9.1 Applications Information
    2. 9.2 Typical Applications
      1. 9.2.1 Connection to an ADC
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Conserving Power Dissipation With Shutdown
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

See (1)(3)
MIN MAX UNIT
Supply voltage –0.3 6 V
Voltage at output pin –0.3 (VDD + 0.5) V
Output current –7 7 mA
Input current at any pin(2) –5 5 mA
Maximum junction temperature (TJMAX) 150 °C
Storage temperature Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > V), the current at that pin should be limited to 5 mA.
(3) Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.

7.2 ESD Ratings

VALUE UNIT
LMT84LP in TO-92/TO-92S package
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(3) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
LMT84DCK in SC70 package
V(ESD) Electrostatic discharge Human-body model (HBM), per JESD22-A114(3) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

7.3 Recommended Operating Conditions

MIN MAX UNIT
Specified temperature TMIN ≤ TA ≤ TMAX  °C
−50 ≤ TA ≤ 150 °C
Supply voltage (VDD) 1.5 5.5 V

7.4 Thermal Information(1)

THERMAL METRIC(2) LMT84/
LMT84-Q1		 LMT84LP LMT84LPG UNIT
DCK (SOT/SC70) LP/LPM (TO-92) LPG (TO-92S)
5 PINS 3 PINS 3 PINS
RθJA Junction-to-ambient thermal resistance (3)(4) 275 167 130.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 84 90 64.2 °C/W
RθJB Junction-to-board thermal resistance 56 146 106.2 °C/W
ψJT Junction-to-top characterization parameter 1.2 35 14.6 °C/W
ψJB Junction-to-board characterization parameter 55 146 106.2 °C/W
(1) For information on self-heating and thermal response time see section Mounting and Thermal Conductivity.
(2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
(3) The junction to ambient thermal resistance (RθJA) under natural convection is obtained in a simulation on a JEDEC-standard, High-K board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are included in the PCB, per JESD 51-5.
(4) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.

7.5 Accuracy Characteristics

These limits do not include DC load regulation. These stated accuracy limits are with reference to the values in Table 3.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
Temperature accuracy (3) 70°C to 150°C; VDD = 1.5 V to 5.5 V –2.7 ±0.6 2.7 °C
0°C to 70°C; VDD = 1.5 V to 5.5 V –2.7 ±0.9 2.7 °C
–50°C to +0°C; VDD = 1.6 V to 5.5 V –2.7 ±0.9 2.7 °C
–50°C to +150°C; VDD = 2.3 V to 5.5 V ±0.4 °C
(1) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
(3) Accuracy is defined as the error between the measured and reference output voltages, tabulated in Table 3 at the specified conditions of supply gain setting, voltage, and temperature (expressed in °C). Accuracy limits include line regulation within the specified conditions. Accuracy limits do not include load regulation; they assume no DC load.

7.6 Electrical Characteristics

Unless otherwise noted, these specifications apply for VDD = +1.5 V to +5.5 V. minimum and maximum limits apply for TA = TJ = TMIN to TMAX; typical values apply for TA = TJ = 25°C.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX (1) UNIT
Sensor gain –5.5 mV/°C
Load regulation (3) Source ≤ 50 μA, (VDD – VOUT) ≥ 200 mV –1 –0.22 mV
Sink ≤ 50 μA, VOUT ≥ 200 mV 0.26 1 mV
Line regulation (4) 200 μV/V
IS Supply current TA = 30°C to 150°C, (VDD – VOUT) ≥ 100 mV 5.4 8.1 μA
TA = –50°C to 150°C, (VDD – VOUT) ≥ 100 mV 5.4 9 μA
CL Output load capacitance 1100 pF
Power-on time (5) CL= 0 pF to 1100 pF 0.7 1.9 ms
Output drive ±50 µA
(1) Limits are specific to TI's AOQL (Average Outgoing Quality Level).
(2) Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
(3) Source currents are flowing out of the LMT84-xx. Sink currents are flowing into the LMT84-xx.
(4) Line regulation (DC) is calculated by subtracting the output voltage at the highest supply voltage from the output voltage at the lowest supply voltage. The typical DC line regulation specification does not include the output voltage shift discussed in Output Voltage Shift.
(5) Specified by design and characterization.

7.7 Typical Characteristics

LMT84 temp_error_vs_temp_nis167.gif Figure 1. Temperature Error vs Temperature
LMT84 supply_current_vs_temp_nis167.gif Figure 3. Supply Current vs Temperature
LMT84 load_reg_sourcing_current_nis167.gif Figure 5. Load Regulation, Sourcing Current
LMT84 change_in_vout_vs_overhead_voltage_nis167.gif Figure 7. Change in Vout vs Overhead Voltage
LMT84 output_voltage_vs_supply_voltage_nis167.gif Figure 9. Output Voltage vs Supply Voltage
LMT84 C002_SNIS167.png Figure 2. Minimum Operating Temperature vs
Supply Voltage
LMT84 supply_current_vs_supply_voltage_nis167.gif Figure 4. Supply Current vs Supply Voltage
LMT84 load_reg_sinking_current_nis167.gif Figure 6. Load Regulation, Sinking Current
LMT84 supply_noise_gain_vs_freq_nis167.gif Figure 8. Supply-Noise Gain vs Frequency
LMT84 D003_SNIS167.gif Figure 10. LMT84LPG Thermal Response vs Common Leaded Thermistor With 1.2-m/s Airflow