Unless otherwise noted, these specifications apply for +VDD = 2.2 V to 5.5 V. MIN and MAX limits apply for TA = TJ = TMIN to TMAX , unless otherwise noted; typical values apply for TA = TJ = 25°C.PARAMETER | TEST CONDITIONS | MIN(1) | TYP(2) | MAX(1) | UNIT |
---|
| Average sensor gain (output transfer function slope) | –30°C and 90°C used to calculate average sensor gain | | –10.9 | | mV/°C |
| Load regulation(3) | Source ≤ 50 μA, (VDD – VOUT) ≥ 200 mV | –1 | –0.22 | | mV |
Sink ≤ 50 μA, VOUT ≥ 200 mV | | 0.26 | 1 | mV |
| Line regulation(4) | | | 200 | | μV/V |
IS | Supply current | TA = 30°C to 150°C, (VDD – VOUT) ≥ 100 mV | | 5.4 | 8.1 | μA |
TA = –50°C to 150°C, (VDD – VOUT) ≥ 100 mV | | 5.4 | 9 | μA |
CL | Output load capacitance | | | 1100 | | pF |
| Power-on time(5) | CL= 0 pF to 1100 pF | | 0.7 | 1.9 | ms |
| Output drive | TA = TJ = 25°C | –50 | | 50 | µA |
(1) Limits are specific to TI's AOQL (Average Outgoing Quality Level).
(2) Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
(3) Source currents are flowing out of the LMT86. Sink currents are flowing into the LMT86.
(4) Line regulation (DC) is calculated by subtracting the output voltage at the
highest supply voltage from the output voltage at the lowest supply voltage. The
typical DC line regulation specification does not include the output voltage
shift discussed in
Output Voltage Shift.
(5) Specified by design and characterization.