LMV11x Low-Voltage, 45-MHz, Rail-To-Rail Output Operational Amplifiers With Shutdown Option
- SNOSA87C October 2003 – October 2016 LMV116 , LMV118
  
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DATA SHEET

LMV11x Low-Voltage, 45-MHz, Rail-To-Rail Output Operational Amplifiers With Shutdown Option

1 Features

−3-dB BW 45 MHz
Supply Voltage Range 2.7 V to 12 V
Slew Rate 40 V/μs
Supply Current 600 μA
Power Down Supply Current 15 μA
Output Short Circuit Current 32 mA
Linear Output Current ±20 mA
Input Common Mode Voltage −0.3 V to 1.7 V
Output Voltage Swing 20 mV from Rails
Input Voltage Noise 40 nV/√Hz
Input Current Noise 0.75 pA/√Hz

2 Applications

High-Speed Clock Buffer/Driver
Active Filters
High-Speed Portable Devices
Multiplexing Applications (LMV118)
Current Sense Amplifier
High-Speed Transducer Amplifier

3 Description

The LMV116 (single) rail-to-rail output voltage feedback amplifiers offer high-speed (45 MHz), and low-voltage operation (2.7 V) in addition to micro-power shutdown capability (LMV118).

Output voltage range extends to within 20 mV of either supply rail, allowing wide dynamic range especially in low voltage applications. Even with low supply current of 600 μA, output current capability is kept at a respectable ±20 mA for driving heavier loads. Important device parameters such as BW, slew rate, and output current are kept relatively independent of the operating supply voltage by a combination of process enhancements and design architecture.

For portable applications, the LMV118 provides shutdown capability while keeping the turnoff current to 15 μA. Both turnon and turnoff characteristics are well behaved with minimal output fluctuations during transitions, thus the device can be used in power-saving mode, as well as multiplexing applications. Miniature packages (5-pin and 6-pin SOT-23) are further means to ease the adoption of these low-power, high-speed devices in applications where board area is at a premium.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LMV116	SOT-23 (5)	2.90 mm × 1.60 mm
LMV116	SOT-23 (6)	2.90 mm × 1.60 mm
LMV118	SOT-23 (5)	2.90 mm × 1.60 mm
LMV118	SOT-23 (6)	2.90 mm × 1.60 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application

4 Revision History

Changes from B Revision (May 2013) to C Revision

Added Device Information and Pin Configuration and Functions sections, ESD Ratings and Thermal Information tables, Functional Block Diagram, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sectionsGo
Changed R_θJA from 265°C/W to 182.7°C/WGo

Changes from A Revision (May 2013) to B Revision

Changed layout of National Semiconductor data sheet to TI formatGo

5 Pin Configuration and Functions

SOT-23 Package

5-Pin DBV

Top View

SOT-23 Package

6-Pin DBV

Top View

Pin Functions

PIN			I/O	DESCRIPTION
NAME	LMV116	LMV118	I/O	DESCRIPTION
+IN	3	3	Input	Non-inverting input
–IN	4	4	Input	Inverting input
OUTPUT	1	1	Output	Output
SD	—	5	Input	Shutdown input. Active high, must be tied to V– with resistor for normal operation.
V+	5	6	Power	Positive (highest) power supply
V–	2	2	Power	Negative (lowest) power supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Supply voltage (V⁺ - V⁻)			12.6	V
Voltage at INPUT and OUTPUT pins		V⁻ −0.8	V⁺ + 0.8	V
Output short-circuit duration		See⁽³⁾, ⁽⁴⁾
Junction temperature⁽⁵⁾			150	°C
Soldering information	Infrared or convection (20 seconds)		235	°C
Soldering information	Wave soldering lead temperature (10 seconds)		260	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications.

(3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C.

(4) Output short circuit duration is infinite for V_S < 6 V at room temperature and below. For V_S > 6 V, allowable short circuit duration is 1.5 ms.

(5) The maximum power dissipation is a function of T_J(MAX), R_θJA, and T_A. The maximum allowable power dissipation at any ambient temperature is P_D = (T_J(MAX) – T_A) / R_θJA . All numbers apply for packages soldered directly onto a PC board.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Machine model	±200	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Supply voltage (V⁺ – V⁻)		2.5		12	V
Temperature⁽¹⁾		−40		85	°C

(1) The maximum power dissipation is a function of T_J(MAX), R_θJA, and T_A. The maximum allowable power dissipation at any ambient temperature is P_D = (T_J(MAX) – T_A)/ R_θJA . All numbers apply for packages soldered directly onto a PC board.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMV116	LMV118	UNIT
		DBV (SOT-23)	DBV (SOT-23)
		5 PINS	6 PINS
R_θJA	Junction-to-ambient thermal resistance	182.7	182.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	139.9	139.9	°C/W
R_θJB	Junction-to-board thermal resistance	41.4	41.4	°C/W
ψ_JT	Junction-to-top characterization parameter	28.5	28.5	°C/W
ψ_JB	Junction-to-board characterization parameter	40.9	40.9	°C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

6.5 Electrical Characteristics: 2.7 V

Unless otherwise specified, all limits apply for T_J = 25°C, V⁺ = 2.7 V, V⁻ = 0 V, V_CM = V_O = V⁺/ 2, and R_F = 2 kΩ, and
R_L = 1 kΩ to V⁺/ 2.

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
V_OS	Input offset voltage	0 V ≤ V_CM ≤ 1.7 V		±1	±5	mV
V_OS	Input offset voltage	0 V ≤ V_CM ≤ 1.7 V –40°C to 85°C			±6
TC V_OS	Input offset average drift	See⁽³⁾		±5		μV/C
I_B	Input bias current	See⁽⁴⁾	−2	−0.4		μA
I_B	Input bias current	See⁽⁴⁾, –40°C to 85°C	–2.2			μA
I_OS	Input offset current			1	500	nA
CMRR	Common mode rejection ratio	V_CMstepped from 0 V to 1.55 V	73	88		dB
PSRR	Power supply rejection ratio	V⁺ = 2.7 V to 3.7 V or V⁻ = 0 V to −1 V	72	85		dB
R_IN	Common mode input resistance			3		MΩ
C_IN	Common mode input capacitance			2		pF
CMVR	Input common-mode voltage range	CMRR ≥ 50 dB	−0.3		1.7	V
CMVR	Input common-mode voltage range	CMRR ≥ 50 dB, –40°C to 85°C	–0.1			V
A_VOL	Large signal voltage gain	V_O = 0.35 V to 2.35 V	73	87		dB
A_VOL	Large signal voltage gain	V_O = 0.35 V to 2.35 V, –40°C to 85°C	70			dB
V_O	Output swing high	R_L = 1 kΩ to V⁺/2	2.55	2.66		V
	Output swing high	R_L = 10 kΩ to V⁺/2		2.68		V
	Output swing low	R_L = 1 kΩ to V⁺/2	150	40		mV
	Output swing low	R_L = 10 kΩ to V⁺/2		20		mV
I_SC	Output short-circuit current	Sourcing to V⁻ V_ID = 200 mV⁽⁵⁾	25	35		mA
I_SC	Output short-circuit current	Sinking to V⁺ V_ID = −200 mV⁽⁵⁾	25	32		mA
I_OUT	Output current	V_OUT = 0.5 V from rails		±20		mA
I_S	Supply current	Normal operation		600	900	μA
I_S	Supply current	Shutdown mode (LMV118)		15	50	μA
SR	Slew rate ⁽⁶⁾	A_V = +1, V_O = 1 V_PP		40		V/μs
BW	−3 dB BW	A_V = +1, V_OUT = 200 mV_PP		45		MHz
e_n	Input-referred voltage noise	f = 100 kHz		40		nV/√Hz
e_n	Input-referred voltage noise	f = 1 kHz		60		nV/√Hz
i_n	Input-referred current noise	f = 100 kHz		0.75		pA/√Hz
i_n	Input-referred current noise	f = 1 kHz		1.2		pA/√Hz
t_on	Turnon time (LMV118)			250		ns
t_off	Turnoff time (LMV118)			560		ns
TH_SD	Shutdown threshold (LMV118)	I_S ≤ 50 μA		1.95	2.3	V
I_SD	SHUTDOWN pin input current (LMV118)	See⁽⁴⁾		−20		μA

(1) All limits are specified by testing or statistical analysis.

(2) Typical values represent the most likely parametric norm.

(3) Offset voltage average drift determined by dividing the change in V_OS at temperature extremes into the total temperature change.

(4) Positive current corresponds to current flowing into the device.

(5) Short-circuit test is a momentary test. See Absolute Maximum Ratings, note 4.

(6) Slew rate is the average of the rising and falling slew rates.

6.6 Electrical Characteristics: 5 V

Unless otherwise specified, all limits apply for T_J = 25°C, V⁺ = 5 V, V⁻ = 0 V, V_CM = V_O = V⁺/2, and R_F = 2 kΩ, and R_L = 1 kΩ to V⁺/2.

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
V_OS	Input offset voltage	0 V ≤ V_CM ≤ 1.7 V		±1	±5	mV
V_OS	Input offset voltage	0 V ≤ V_CM ≤ 1.7 V –40°C to 85°C			±6	mV
TC V_OS	Input offset average drift	See⁽³⁾		±5		μV/C
I_B	Input bias current	See⁽⁴⁾	−2	−0.4		μA
I_B	Input bias current	See⁽⁴⁾, –40°C to 85°C	–2.2			μA
I_OS	Input offset current			1	500	nA
CMRR	Common mode rejection ratio	V_CMstepped from 0 V to 3.8 V	77	85		dB
PSRR	Power supply rejection ratio	V⁺ = 5 V to 6 V or V⁻ = 0 V to −1 V	72	95		dB
R_IN	Common mode input resistance			3		MΩ
C_IN	Common mode input capacitance			2		pF
CMVR	Input common-mode voltage range	CMRR ≥ 50 dB	−0.3		4	V
CMVR	Input common-mode voltage range	CMRR ≥ 50 dB, –40°C to 85°C	–0.1			V
A_VOL	Large signal voltage gain	V_O = 1.5 V to 3.5 V	73	87		dB
A_VOL	Large signal voltage gain	V_O = 1.5 V to 3.5 V, –40°C to 85°C	70			dB
V_O	Output swing high	R_L = 1 kΩ to V⁺/2	4.8	4.95		V
	Output swing high	R_L = 10 kΩ to V⁺/2		4.98		V
	Output swing low	R_L = 1 kΩ to V⁺/2	200	50		mV
	Output swing low	R_L = 10 kΩ to V⁺/2		20		mV
I_SC	Output short-circuit current	Sourcing to V⁻ V_ID = 200 mV⁽⁵⁾	35	45		mA
I_SC	Output short-circuit current	Sinking to V⁺ V_ID = –200 mV⁽⁵⁾	35	43		mA
I_OUT	Output current	V_OUT = 0.5 V from rails		±20		mA
I_S	Supply current	Normal operation		600	900	μA
I_S	Supply current	Shutdown mode (LMV118)		10	50	μA
SR	Slew rate ⁽⁶⁾	A_V = +1, V_O = 1 V_PP		40		V/μs
BW	−3 dB BW	A_V = +1, V_OUT = 200 mV_PP		45		MHz
e_n	Input-referred voltage noise	f = 100 kHz		40		nV/√Hz
e_n	Input-referred voltage noise	f = 1 kHz		60		nV/√Hz
i_n	Input-referred current noise	f = 100 kHz		0.75		pA/√Hz
i_n	Input-referred current noise	f = 1 kHz		1.2		pA/√Hz
t_on	Turnon time (LMV118)			210		ns
t_off	Turnoff time (LMV118)			500		ns
TH_SD	Shutdown threshold (LMV118)	I_S ≤ 50 μA		4.25	4.6	V
I_SD	SHUTDOWN pin input current (LMV118)	See⁽⁴⁾		−20		μA

(1) All limits are specified by testing or statistical analysis.

(2) Typical values represent the most likely parametric norm.

(3) Offset voltage average drift determined by dividing the change in V_OS at temperature extremes into the total temperature change.

(4) Positive current corresponds to current flowing into the device.

6.7 Electrical Characteristics: ±5 V

Unless otherwise specified, all limits apply for T_J = 25°C, V⁺ = 5 V, V⁻ = –5 V, V_CM = V_O = 0 V, and R_F = 2 kΩ, and R_L = 1 kΩ to V⁺/2.

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
V_OS	Input offset voltage	0 V ≤ V_CM ≤ 1.7 V		±1	±5	mV
V_OS	Input offset voltage	0 V ≤ V_CM ≤ 1.7 V –40°C to 85°C			±6	mV
TC V_OS	Input offset average drift	See⁽³⁾		±5		μV/C
I_B	Input bias current	See⁽⁴⁾	−2	−0.4		μA
I_B	Input bias current	See⁽⁴⁾, –40°C to 85°C	–2.2			μA
I_OS	Input offset current			3	500	nA
CMRR	Common mode rejection ratio	V_CMstepped from 0 V to 3.8 V	78	104		dB
PSRR	Power supply rejection ratio	V⁺ = 5 V to 6 V or V⁻ = 0 V to −1 V	72	95		dB
R_IN	Common mode input resistance			3		MΩ
C_IN	Common mode input capacitance			2		pF
CMVR	Input common-mode voltage range	CMRR ≥ 50 dB	−5.3		4	V
CMVR	Input common-mode voltage range	CMRR ≥ 50 dB, –40°C to 85°C	–5.1			V
A_VOL	Large signal voltage gain	V_O = 1.5 V to 3.5 V	74	85		dB
A_VOL	Large signal voltage gain	V_O = 1.5 V to 3.5 V, –40°C to 85°C	71			dB
V_O	Output swing high	R_L = 1 kΩ to V⁺/2	4.7	4.92		V
	Output swing high	R_L = 10 kΩ to V⁺/2		4.97		V
	Output swing low	R_L = 1 kΩ to V⁺/2	–4.7	–4.92		V
	Output swing low	R_L = 10 kΩ to V⁺/2		–4.98		V
I_SC	Output short-circuit current	Sourcing to V⁻ V_ID = 200 mV⁽⁵⁾	40	57		mA
I_SC	Output short-circuit current	Sinking to V⁺ V_ID = −200 mV⁽⁵⁾	40	54		mA
I_OUT	Output current	V_OUT = 0.5 V from rails		±20		mA
I_S	Supply current	Normal operation		600	900	μA
I_S	Supply current	Shutdown mode (LMV118)		15	50	μA
SR	Slew rate ⁽⁶⁾	A_V = 1, V_O = 1 V_PP		35		V/μs
BW	−3 dB BW	A_V = 1, V_OUT = 200 mV_PP		45		MHz
e_n	Input-referred voltage noise	f = 100 kHz		40		nV/√Hz
e_n	Input-referred voltage noise	f = 1 kHz		60		nV/√Hz
i_n	Input-referred current noise	f = 100 kHz		0.75		pA/√Hz
i_n	Input-referred current noise	f = 1 kHz		1.2		pA/√Hz
t_on	Turnon time (LMV118)			200		ns
t_off	Turnoff time (LMV118)			700		ns
TH_SD	Shutdown threshold (LMV118)	I_S ≤ 50 μA		4.25	4.6	V
I_SD	SHUTDOWN pin input current (LMV118)	See⁽⁴⁾		−20		μA

(1) Typical values represent the most likely parametric norm.

(2) Offset voltage average drift determined by dividing the change in V_OS. All limits are specified by testing or statistical analysis.

(3) at temperature extremes into the total temperature change.

(4) Positive current corresponds to current flowing into the device.

(5) Short-circuit test is a momentary test. See Absolute Maximum Ratings, note 4.

6.8 Typical Characteristics

At T_J = 25°C. Unless otherwise specified.

Figure 1. Supply Current vs Supply Voltage

Figure 3. Gain and Phase vs Frequency

Figure 5. PSRR vs Frequency

Figure 7. Input Current Noise vs Frequency

Figure 9. Frequency Response For Various (A_V)

Figure 11. Offset Voltage vs Common Mode Voltage
(a Typical Unit)

Figure 13. Offset Voltage vs Common Mode Range
(a Typical Unit)

Figure 15. Input Bias Current vs V_CM

Figure 17. Sink Current vs V_OUT

Figure 19. Source Current vs V_OUT

Figure 2. Supply Current vs V_CM

Figure 4. CMRR vs Frequency

Figure 6. Input Voltage Noise vs Frequency

Figure 8. Closed-Loop Frequency Response for Various Temperature

Figure 10. Large Signal Step Response

Figure 12. Offset Voltage vs Common Mode Voltage (a Typical Unit)

Figure 14. Input Bias Current vs Supply Voltage

Figure 16. Sink Current vs V_OUT

Figure 18. Souce Current vs V_OUT

7 Detailed Description

7.1 Overview

The LMV116 and LMV118 are based on TI’s proprietary VIP10 dielectrically isolated bipolar process.

The LMV116 and LMV118 architecture features the following:

Complementary bipolar devices with exceptionally high f_t (approximately 8 GHz) even under low supply voltage (2.7 V) and low collector bias current.
Common emitter push-pull output stage capable of 20-mA output current (at 0.5 V from the supply rails) while consuming only 600 μA of total supply current. This architecture allows output to reach within milli-volts of either supply rail at light loads.
Consistent performance from any supply voltage (2.7 V to 10 V) with little variation with supply voltage for the most important specifications (for example, BW, SR, I_OUT, etc.)

7.2 Functional Block Diagram

LMV116 LMV118 functional_block_diagram_snosa87.gif

7.3 Feature Description

The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (–IN). The amplifier amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The output voltage of the op-amp V_OUT is given by Equation 1:

Equation 1. V_OUT = A_VOL (+IN – –IN)

where

A_VOL is the open-loop gain of the amplifier, typically around 85 dB.

7.4 Device Functional Modes

7.4.1 Quasi-Saturated State

When the output swing approaches either supply rail, the output transistor enters a quasi-saturated state. A subtle effect of this operational region is that there is an increase in supply current in this state (up to 1 mA). The onset of quasi-saturation region is a function of output loading (current) and varies from 100 mV at no load to about 1 V when output is delivering 20 mA, as measured from supplies. Both input common mode voltage and output voltage level affect the supply current (see Typical Characteristics for plot).

7.4.2 Micro-Power Shutdown

The LMV118 can be shut down to save power and reduce its supply current to less than the 50 μA specified by applying a voltage to the SD pin. The SD pin is active high and needs to be tied to V⁻ for normal operation. This input is low current (< 20-μA, 4-pF equivalent capacitance) and a resistor to V⁻ (≤ 20 kΩ) results in normal operation. Shutdown is specified when SD pin is 0.4 V or less from V⁺ at any operating supply voltage and temperature.

In the shutdown mode, essentially all internal device biasing is turned off in order to minimize supply current flow, and the output goes into Hi-Z (high impedance) mode. Complete device turnon and turnoff times vary considerably relative to the output loading conditions, output voltage, and input impedance, but is generally limited to less than 1 μs (see Electrical Characteristics: 2.7 V, Electrical Characteristics: 5 V, and Electrical Characteristics: ±5 V)

During shutdown, the input stage has an equivalent circuit as shown in Figure 20.

Figure 20. Input Stage Shutdown Equivalent Circuit

As can be seen from Figure 20, in shutdown there may be current flow through the internal diodes shown, caused by input potential, if present. This current may flow through the external feedback resistor and result in an apparent output signal. In most shutdown applications the presence of this output is inconsequential. However, if the output is forced by another device such as in a multiplexer, the other device must conduct the current described in order to maintain the output potential.

To keep the output at or near ground during shutdown when there is no other device to hold the output low, a switch (transistor) could be used to shunt the output to ground. Figure 21 shows a circuit where a NPN bipolar is used to keep the output near ground (approximately 80 mV):

Figure 21. Active Pulldown Schematic

Figure 22 shows the output waveform.

Figure 22. Output Held Low by Active Pulldown Circuit

If bipolar transistor power dissipation is not tolerable, the switch can be done by an N-channel enhancement-mode MOSFET.