SNOSA87C October   2003  – October 2016 LMV116 , LMV118

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: 2.7 V
    6. 6.6 Electrical Characteristics: 5 V
    7. 6.7 Electrical Characteristics: ±5 V
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Quasi-Saturated State
      2. 7.4.2 Micro-Power Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: 2.7-V Single Supply 2:1 MUX
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Generally, a good high-frequency layout keeps power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground cause frequency response peaking and possible circuit oscillations (see OA-15 Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers for more information).

TI suggests the following evaluation boards as a guide for high-frequency layout and as an aid in device testing and characterization:

DEVICE PACKAGE EVALUATION BOARD P/N
LMV116 SOT-23-5 CLC730068
LMV118 SOT-23-6 CLC730116

10.2 Layout Example

LMV116 LMV118 layout.gif Figure 25. LMV116/LMV118 Layout