at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
Figure 5-1 IB and IOS vs Temperature Figure 5-3 Open-Loop Gain vs Temperature Figure 5-5 Open-Loop Gain vs Output Voltage Figure 5-2 IB and IOS vs Common-Mode Voltage Figure 5-4 Open-Loop Gain and Phase vs Frequency Figure 5-6 Closed-Loop Gain vs Frequency Figure 5-7 Output Voltage vs Output Current (Claw) Figure 5-9 DC PSRR vs Temperature | VCM = (V–) – 0.1 V to (V+) – 1.4 V | |
Figure 5-11 DC CMRR vs TemperatureFigure 5-8 PSRR vs Frequency Figure 5-10 CMRR vs Frequency Figure 5-12 0.1 Hz to 10 Hz Integrated Voltage Noise Figure 5-13 Input Voltage Noise Spectral Density VS = 5.5 V, VCM = 2.5 V, f = 1 kHz, G = 1, BW = 80 kHz |
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Figure 5-15 THD + N vs AmplitudeFigure 5-17 Quiescent Current vs Temperature VS = 5.5 V, VCM = 2.5 V, G = 1, BW = 80 kHz, VOUT = 0.5 VRMS |
Figure 5-14 THD + N vs FrequencyFigure 5-16 Quiescent Current vs Supply Voltage Figure 5-18 Open-Loop Output Impedance vs Frequency Figure 5-19 Small Signal Overshoot vs Capacitive Load Figure 5-21 Phase Margin vs Capacitive Load Figure 5-23 Overload Recovery Figure 5-20 Small Signal Overshoot vs Capacitive Load Figure 5-22 No Phase Reversal G = 1, VIN = 100 mVPP, CL = 10 pF |
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Figure 5-24 Small-Signal Step ResponseG = 1, VIN = 4 VPP, CL = 10 pF |
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Figure 5-25 Large-Signal Step ResponseG = 1, CL = 100 pF, 2-V step |
Figure 5-27 Large-Signal Settling Time (Positive)Figure 5-29 Maximum Output Voltage vs Frequency Figure 5-31 Channel Separation G = 1, CL = 100 pF, 2-V step |
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Figure 5-26 Large-Signal Settling Time (Negative)Figure 5-28 Short-Circuit Current vs Temperature Figure 5-30 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency