7.3.1 Input and Output Stage

The rail-to-rail input stage of this family provides more flexibility for the designer. The LMV61x use a complimentary PNP and NPN input stage in which the PNP stage senses common-mode voltage near V⁻ and the NPN stage senses common-mode voltage near V⁺. The transition from the PNP stage to NPN stage occurs
1 V below V⁺. Because both input stages have their own offset voltage, the offset of the amplifier becomes a function of the input common-mode voltage and has a crossover point at 1 V below V⁺.

This V_OS crossover point can create problems for both DC- and AC-coupled signals if proper care is not taken. Large input signals that include the V_OS crossover point causes distortion in the output signal. One way to avoid such distortion is to keep the signal away from the crossover. For example, in a unity-gain buffer configuration and with V_S = 5 V, a 5-V peak-to-peak signal contains input-crossover distortion while a 3-V peak-to-peak signal centered at 1.5 V does not contain input-crossover distortion as it avoids the crossover point. Another way to avoid large signal distortion is to use a gain of −1 circuit which avoids any voltage excursions at the input terminals of the amplifier. In that circuit, the common-mode DC voltage can be set at a level away from the V_OS crossover point. For small signals, this transition in V_OS shows up as a V_CM dependent spurious signal in series with the input signal and can effectively degrade small signal parameters such as gain and common-mode rejection ratio. To resolve this problem, the small signal must be placed such that it avoids the V_OS crossover point. In addition to the rail-to-rail performance, the output stage can provide enough output current to
drive 600-Ω loads. Because of the high current capability, take care to not exceed the 150°C maximum junction temperature specification.

7.4.1 Input Bias Current Consideration

The LMV61x family has a complementary bipolar input stage. The typical input bias current (I_B) is 15 nA. The input bias current can develop a significant offset voltage. This offset is primarily due to I_B flowing through the negative feedback resistor, R_F. For example, if I_B is 50 nA and R_F is 100 kΩ, then an offset voltage of 5 mV develops (V_OS = I_B × R_F). Using a compensation resistor (R_C), as shown in Figure 29, cancels this effect. But the input offset current (I_OS) still contributes to an offset voltage in the same manner.

Figure 29. Canceling Offset Voltage Due to Input Bias Current