SLOS969A June   2017  – January 2018 LMV722-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics VCC+ = 2.2 V
    6. 6.6 Electrical Characteristics VCC+ = 5 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low Noise
      2. 7.3.2 Rail-to-Rail Output
      3. 7.3.3 Input Includes Ground
      4. 7.3.4 Signal Integrity
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Input and ESD Protection
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics VCC+ = 5 V

VCC+ = 5 V, VCC− = GND, VICR = VCC+/2, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VIO Input offset voltage TJ = 25°C –0.08 3 mV
TJ = –40°C to +125°C 3.5
TCVIO Input offset voltage average drift TJ = 25°C 0.6 μV/°C
IIB Input bias current TJ = 25°C 260 nA
IIO Input offset current TJ = 25°C 25 nA
CMMR Common-mode rejection ratio VICR = 0 V to 4.1 V TJ = 25°C 80 89 dB
VICR = 0 V to 4.1 V TJ = –40°C to +125°C 75
PSRR Power-supply rejection ratio VCC+ = 2.2 V to 5 V,
VO = 0, VICR = 0		 TJ = 25°C 70 90 dB
VCC+ = 2.2 V to 5 V,
VO = 0, VICR = 0		 TJ = –40°C to +125°C 64
VICR Input common-mode voltage CMRR ≥ 50 dB TJ = 25°C –0.3 V
TJ = 25°C 4.1
AVD Large-signal voltage gain RL = 600 Ω,
VO = 0.75 V to 4.8 V 		TJ = 25°C 80 87 dB
TJ = –40°C to +125°C 70
RL = 2 kΩ,
VO = 0.7 V to 4.9 V 		TJ = 25°C 80 94
TJ = –40°C to +125°C 70
VO Output swing RL = 600 Ω to VCC+/2 TJ = 25°C 4.84 4.882 V
TJ = –40°C to +125°C 4.815
TJ = 25°C 0.134 0.19
TJ = –40°C to +125°C 0.215
RL = 2 kΩ to VCC+/2 TJ = 25°C 4.93 4.952
TJ = –40°C to +125°C 4.905
TJ = 25°C 0.076 0.11
TJ = –40°C to +125°C 0.135
IO Output current Sourcing, VO = 0 V,
VIN(diff) = ±0.5 V		 TJ = 25°C 20 52.6 mA
TJ = –40°C to +125°C 12
Sinking, VO = 2.2 V,
VIN(diff) = ±0.5 V		 TJ = 25°C 15 23.7
TJ = –40°C to +125°C 8.5
ICC Supply current TJ = 25°C 2.01 2.4 mA
TJ = –40°C to +125°C 2.8
SR Slew rate(1) TJ = 25°C 5.25 V/μs
GBW Gain bandwidth product TJ = 25°C 10 MHz
Φm Phase margin TJ = 25°C 72 °
Gm Gain margin TJ = 25°C –11 dB
Vn Input-referred voltage noise f = 1 kHz TJ = 25°C 10.5 nV/√Hz
In Input-referred current noise f = 1 kHz TJ = 25°C 0.2 pA/√Hz
THD Total harmonic distortion f = 1 kHz, AV = 1,
RL = 600 Ω, VO = 500 mVpp		 TJ = 25°C 0.001%
(1) Connected as voltage follower with 1-V step input. Number specified is the slower of the positive and negative slew rate.