The LMV727x devices are rail-to-rail input low power comparators, characterized at supply voltages 1.8 V, 2.7 V, and 5 V. They consume as little as 9-uA supply current per channel while achieving a 800-ns propagation delay.
The LMV7271 and LMV7275 (single) are available in SC70 and SOT-23 packages. The LMV7272 (dual) is available in the DSBGA package. With these tiny packages, the PCB area can be significantly reduced. They are ideal for low voltage, low power, and space-critical designs.
The LMV7271 and LMV7272 both feature a push-pull output stage which allows operation with minimum power consumption when driving a load.
The LMV7275 features an open-drain output stage that allows for wired-OR configurations. The open-drain output also offers the advantage of allowing the output to be pulled to any voltage up to 5.5 V, regardless of the supply voltage of the LMV7275, which is useful for level-shifting applications.
The LMV727x devices are built with Texas Instruments' advance submicron silicon-gate BiCMOS process. They all have bipolar inputs for improved noise performance, and CMOS outputs for rail-to-rail output swing.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMV7271, LMV7275 |
SC70 (5) | 1.25 mm × 2.00 mm |
SOT-23 (5) | 1.60 mm × 2.90 mm | |
LMV7272 | DSBGA (8) | 1.50 mm x 1.50 mm |
Changes from H Revision (February 2013) to I Revision
Changes from G Revision (February 2013) to H Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOT-23, SC70 | DSBGA | ||
+IN | 1 | — | I | Noninverting Input |
GND | 2 | — | P | Negative Supply Voltage |
-IN | 3 | — | I | Invering Input |
VOUT | 4 | — | O | Output |
V+ | 5 | A2 | P | Positive Supply Voltage |
OUT A | — | A1 | O | Output, Channel A |
-IN A | — | B1 | I | Inverting Input, Channel A |
+IN A | — | C1 | I | Noninverting Input, Channel A |
V- | — | C2 | P | Negative Supply Voltage |
+IN B | — | C3 | I | Noninverting Input, Channel B |
-IN B | — | B3 | I | Inverting Input, Channel B |
OUT B | — | A3 | O | Output, Channel B |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN Differential | ±Supply Voltage | V | ||
Supply Voltage (V+ - V−) | 6 | V | ||
Voltage at Input/Output pins | (V+) + 0.1 | (V−) − 0.1 | V | |
Junction Temperature(3) | 150 | °C | ||
Storage Temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
SOT-23, SC70 PACKAGE | ||||
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) | ±2000 | V |
Machine Model (MM)(3) | ±200 | |||
DSBGA PACKAGE | ||||
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) | ±2000 | V |
Machine Model (MM)(3) | ±200 |
MIN | MAX | UNIT | |
---|---|---|---|
Supply Voltage | 1.8 | 5.5 | V |
Temperature(1) | –40 | 85 | °C |
THERMAL METRIC(1) | LMV7271, LMV7275 | LMV7272 | UNIT | ||
---|---|---|---|---|---|
DBV (SOT-23) | DGK (SC70) | YZR (DSBGA) | |||
5 PINS | 5 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance(2) | 325 | 265 | 220 | °C/W |
PARAMETER | CONDITION | MIN(2) | TYP(1) | MAX(2) | UNIT | ||
---|---|---|---|---|---|---|---|
VOS | Input Offset Voltage | 0.3 | 4 | mV | |||
At the temperature extremes | 6 | ||||||
TC VOS | Input Offset Temperature Drift | VCM = 0.9 V (3) | 20 | uV/°C | |||
IB | Input Bias Current | 10 | nA | ||||
IOS | Input Offset Current | 200 | pA | ||||
IS | Supply Current | LMV7271/LMV7275 | 9 | 12 | µA | ||
At the temperature extremes | 14 | ||||||
LMV7272 | 18 | 25 | µA | ||||
At the temperature extremes | 28 | ||||||
ISC | Output Short Circuit Current | Sourcing, VO = 0.9 V (LMV7271/LMV7272 only) |
3.5 | 6 | mA | ||
Sinking, VO = 0.9 V | 4 | 6 | |||||
VOH | Output Voltage High (LMV7271/LMV7272 only) |
IO = 0.5 mA | 1.7 | 1.74 | V | ||
IO = 1.5 mA | 1.47 | 1.63 | |||||
VOL | Output Voltage Low | IO = −0.5 mA | 52 | 100 | mV | ||
IO = −1.5 mA | 166 | 220 | |||||
VCM | Input Common-Mode Voltage Range | CMRR > 45 dB | 1.9 | V | |||
−0.1 | V | ||||||
CMRR | Common-Mode Rejection Ratio | 0 < VCM < 1.8 V | 46 | 78 | dB | ||
PSRR | Power Supply Rejection Ratio | V+ = 1.8 V to 5 V | 55 | 80 | dB | ||
ILEAKAGE | Output Leakage Current | VO = 1.8 V (LMV7275 only) | 2 | pA |
PARAMETER | CONDITION | MIN(2) | TYP(1) | MAX(2) | UNIT | |
---|---|---|---|---|---|---|
tPHL | Propagation Delay (High to Low) |
Input Overdrive = 20 mV Load = 50 pF//5 kΩ |
880 | ns | ||
Input Overdrive = 50 mV Load = 50 pF//5 kΩ |
570 | ns | ||||
tPLH | Propagation Delay (Low to High) |
Input Overdrive = 20 mV Load = 50 pF//5 kΩ |
1100 | ns | ||
Input Overdrive = 50 mV Load = 50 pF//5 kΩ |
800 | ns |
PARAMETER | CONDITIONS | MIN(2) | TYP(1) | MAX(2) | UNIT | ||
---|---|---|---|---|---|---|---|
VOS | Input Offset Voltage | 0.3 | 4 | mV | |||
At the temperature extremes | 6 | ||||||
TC VOS | Input Offset Temperature Drift | VCM = 1.35 V(3) | 20 | µV/°C | |||
IB | Input Bias Current | 10 | nA | ||||
IOS | Input offset Current | 200 | pA | ||||
IS | Supply Current | LMV7271/LMV7275 | 9 | 13 | µA | ||
At the temperature extremes | 15 | ||||||
LMV7272 | 18 | 25 | µA | ||||
At the temperature extremes | 28 | ||||||
ISC | Output Short Circuit Current | Sourcing, VO = 1.35 V (LMV7271/LMV7272 only) |
10 | 15 | mA | ||
Sinking, VO = 1.35 V | 10 | 15 | |||||
VOH | Output Voltage High (LMV7271/LMV7272 only) |
IO = 0.5 mA | 2.63 | 2.66 | V | ||
IO = 2.0 mA | 2.48 | 2.55 | |||||
VOL | Output Voltage Low | IO = −0.5 mA | 50 | 70 | mV | ||
IO = −2 mA | 155 | 220 | |||||
VCM | Input Common Voltage Range | CMRR > 45 dB | 2.8 | V | |||
−0.1 | V | ||||||
CMRR | Common-Mode Rejection Ratio | 0 < VCM < 2.7 V | 46 | 78 | dB | ||
PSRR | Power Supply Rejection Ratio | V+ = 1.8 V to 5 V | 55 | 80 | dB | ||
ILEAKAGE | Output Leakage Current | VO = 2.7 V (LMV7275 only) | 2 | pA |
PARAMETER | CONDITION | MIN(2) | TYP(1) | MAX(2) | UNIT | |
---|---|---|---|---|---|---|
tPHL | Propagation Delay (High to Low) |
Input Overdrive = 20 mV Load = 50 pF//5 kΩ |
1200 | ns | ||
Input Overdrive = 50 mV Load = 50 pF//5 kΩ |
810 | ns | ||||
tPLH | Propagation Delay (Low to High) |
Input Overdrive = 20 mV Load = 50 pF//5 kΩ |
1300 | ns | ||
Input Overdrive = 50 mV Load = 50 pF//5 kΩ |
860 | ns |
PARAMETER | CONDITIONS | MIN(2) | TYP(1) | MAX(2) | UNIT | ||
---|---|---|---|---|---|---|---|
VOS | Input Offset Voltage | 0.3 | 4 | mV | |||
At the temperature extremes | 6 | ||||||
TC VOS | Input Offset Temperature Drift | VCM = 2.5 V(3) | 20 | µV/°C | |||
IB | Input Bias Current | 10 | nA | ||||
IOS | Input Offset Current | 200 | pA | ||||
IS | Supply Current | LMV7271/LMV7275 | 10 | 14 | µA | ||
At the temperature extremes | 16 | ||||||
LMV7272 | 20 | 27 | µA | ||||
At the temperature extremes | 30 | ||||||
ISC | Output Short Circuit Current | Sourcing, VO = 2.5 V (LMV7271/LMV7272 only) |
18 | 34 | mA | ||
Sinking, VO = 2.5 V | 18 | 34 | |||||
VOH | Output Voltage High (LMV7271/LMV7272 only) |
IO = 0.5 mA | 4.93 | 4.96 | V | ||
IO = 4.0 mA | 4.675 | 4.77 | |||||
VOL | Output Voltage Low | IO = −0.5 mA | 27 | 70 | mV | ||
IO = −4.0 mA | 225 | 315 | |||||
VCM | Input Common Voltage Range | CMRR > 45 dB | 5.1 | V | |||
−0.1 | |||||||
CMRR | Common-Mode Rejection Ratio | 0 < VCM < 5.0 V | 46 | 78 | dB | ||
PRSS | Power Supply Rejection Ratio | V+ = 1.8 V to 5 V | 55 | 80 | dB | ||
ILEAKAGE | Output Leakage Current | VO = 5 V (LMV7275 only) | 2 | pA |
PARAMETER | CONDITION | MIN(2) | TYP(1) | MAX(2) | UNIT | |
---|---|---|---|---|---|---|
tPHL | Propagation Delay (High to Low) |
Input Overdrive = 20 mV Load = 50 pF//5 kΩ |
2100 | ns | ||
Input Overdrive = 50 mV Load = 50 pF//5 kΩ |
1380 | ns | ||||
tPLH | Propagation Delay (Low to High) |
Input Overdrive = 20 mV Load = 50 pF//5 kΩ |
1800 | ns | ||
Input Overdrive = 50 mV Load = 50 pF//5 kΩ |
1100 | ns |
A comparator is often used to convert an analog signal to a digital signal. As shown in Figure 24, the comparator compares an input voltage (VIN) to a reference voltage (VREF). If VIN is less than VREF, the output (VO) is low. However, if VIN is greater than VREF, the output voltage (VO) is high.
The LMV727X has an input common mode voltage range (VCM) of −0.1V below the V− to 0.1 V above V+. This is achieved by using paralleled PNP and NPN differential input pairs. When the VCM is near V+, the NPN pair is on and the PNP pair is off. When the VCM is near V−, the NPN pair is off and the PNP pair is on. The crossover point between the NPN and PNP input stages is around 950mV from V+. Because each input stage has its own offset voltage (VOS), the VOS of the comparator becomes a function of the VCM. See curves for VOS vs. VCM in the Typical Characteristics section. In application design, it is recommended to keep the VCM away from the crossover point to avoid problems. The wide input voltage range makes LMV727X ideal in power supply monitoring circuits, where the comparators are used to sense signals close to ground and power supplies.
The LMV7271 and LMV7272 have a push-pull output stage. This output stage keeps the total system power consumption to the absolute minimum by eliminating the need for a pullup resistor. The only current consumed is the low supply current and the current going directly into the load.
When the output switches, both PMOS and NMOS at the output stage are on at the same time for a very short time. This allows current to flow directly between V+ and V− through output transistors. The result is a short spike of current (called shoot-through current) drawn from the supply and glitches in the supply voltages. The glitches can spread to other parts of the board as noise. To prevent the glitches in supply lines, power supply bypass capacitors must be installed. See Circuit Techniques for Avoiding Oscillations in Comparator Applications for supply bypassing for details.
The LMV7275 has an open-drain output that requires a pullup resistor to a positive supply voltage for the output to operate properly. The internal circuitry is identical to the LMV7271 except that the upper P-channel output device is absent. When the internal output transistor is off, the output voltage will be pulled up to the external positive voltage by the external pullup resistor. This allows the output to be OR'ed with other open-drain outputs on the same bus. The output pullup resistor may be connected to any voltage level between V- and V+ for level shifting applications.
The propagation delay is not affected by capacitive loads at the output of the LMV7271 or LMV7272. However, resistive loads slightly effect the propagation delay on the falling edge depending on the load resistance value.
The propagation delay on the rising edge of the LMV7275 depends on the load resistance and capacitance values.
Most comparators have rather low gain. This allows the output to alternate between high and low when the input signal changes slowly. The result is the output may oscillate between high and low when the differential input is near zero and triggers on noise. The high gain of this comparator eliminates this problem. Less than 1 μV of change on the input will drive the output from one rail to the other rail. If the input signal is noisy, the output cannot ignore the noise unless some hysteresis is provided by positive feedback. (See Hysteresis.)
It is a standard procedure to use hysteresis (positive feedback) around a comparator to prevent oscillation due to the comparator triggering its own noise on slowly ramping signals. The following sections will describe various ways to apply hysteresis.
A noninverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the inverting input. When VIN is low, the output is also low. For the output to switch from low to high, VIN must rise up to VIN1 where VIN1 is calculated by:
As soon as VO switches to VCC, VA steps to a value greater than VREF which is given by:
To make the comparator switch back to its low state, VIN must equal VREF before VA will again equal VREF. VIN2 can be calculated by:
The hysteresis of this circuit is the difference between VIN1 and VIN2.
The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage VCC of the comparator (Figure 29). When VIN at the inverting input is less than VA, the voltage at the noninverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VO switches as high as VCC). The three network resistors can be represented as R1||R3 in series with R2. The lower input trip voltage VA1 is defined as
When VIN is greater than VA (VIN > VA), the output voltage is low and very close to ground. In this case the three network resistors can be presented as R2//R3 in series with R1. The upper trip voltage VA2 is defined as
The total hysteresis provided by the network is defined as
A good typical value of ΔVA would be in the range of 5 to 50 mV. This is easily obtained by choosing R3 as 1000 to 100 times (R1||R2) for 5-V operation, or as 300 to 30 times (R1||R2) for 1.8-V operation.
In a zero crossing detector circuit, the inverting input is connected to ground and the noninverting input is connected to a 100 mVPP AC signal. As the signal at the noninverting input crosses 0 V, the output of the comparator changes state.
To improve switching times and centering the input threshold to ground a small amount of positive feedback is added to the circuit. Voltage divider R4 and R5 establishes a reference voltage, V1, at the positive input. By making the series resistance, R1 plus R2 equal to R5, the switching condition, V1 = V2, will be satisfied when VIN = 0.
The positive feedback resistor, R6, is made very large with respect to R5 || R6 = 2000 R5). The resultant hysteresis established by this network is very small (ΔV1 < 10 mV) but it is sufficient to insure rapid output voltage transitions.
Diode D1 is used to insure that the inverting input terminal of the comparator never goes below approximately −100 mV. As the input terminal goes negative, D1 will forward bias, clamping the node between R1 and R2 to approximately −700 mV. This sets up a voltage divider with R2 and R3 preventing V2 from going below ground. The maximum negative input overdrive is limited by the current handling ability of D1.
Instead of tying the inverting input to 0 V, the inverting input can be tied to a reference voltage. As the input on the noninverting input passes the VREF threshold, the output of the comparator changes state. It is important to use a stable reference voltage to ensure a consistent switching point.
The output of LMV7275 is an unconnected drain of an NMOS device, which can be pulled up, through a resistor, to any desired output level within the permitted power supply range. Hence, the following simple circuit works as a universal logic level shifter, pulling up the signal to the desired level.
For example, VA could be the 5-V analog supply voltage, where VB could be the 3.3-V supply of the processor. The output will now be compatable with the 3.3-V logic.
Because the LMV7275 output is an unconnected NMOS drain, many open-drain outputs can be tied together, pulled up to V+ by a common resistor to provide an output OR'ing function. If any of the comparator outputs goes low, the output VO goes low.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LMV727x devices are single-supply comparators with 880 ns of propagation delay and only 12 µA of supply current.
A typical application for a comparator is as a square wave oscillator. Figure 35 generates a square wave whose period is set by the RC time constant of the capacitor C1and resistor R4. The maximum frequency is limited by the large signal propagation delay of the comparator, and by the capacitive loading at the output, which limits the output slew rate.
To analyze the circuit, consider it when the output is high. That implies that the inverted input (VC) is lower than the noninverting input (VA).
This causes the C1 to get charged through R4, and the voltage VC increases till it is equal to the noninverting input. The value of VA at this point is
If R1 = R2 = R3, then VA1 = 2VCC/3
At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is
If R1 = R2 = R3, then VA2 = VCC/3
The capacitor C1 now discharges through R4, and the voltage VC decreases till it is equal to VA2, at which point the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1.ln2. Hence the formula for the frequency is:
Figure Figure 37 shows the simulated results of an oscillator using the following values:
The positive peak detect circuit is basically a comparator operated in a unity gain follower configuration, with a capacitor as a load to store the highest voltage. A diode is added at the output to prevent the capacitor from discharging through the pullup resistor. When the input VIN increases, the inverting input of the comparator follows it, thus charging the capacitor. When the input voltage decreases, the cap discharges through the 1-MΩ resistor.
The decay time can be modified by changing R2. The output should be accessed through a high-impedance input follower circuit to prevent loading. Upper output swing headroom is determined by the forward voltage of the diode (VMAX = VCC – VF). A Shottky signal diode can be used to reduce the required headroom to around 300 mV.
This circuit can use any of the LMV727x devices, but R1 is not required for the LMV7271 or LMV7272.
The Negative Peak Detector circuit will store the peak negative voltage below ground ( 0 V to –VCC). For the negative detector, the LMV7275 must be used because the output transistor acts as a low-impedance current sink. Because there is no pullup resistor, the only discharge path will be the 1-MΩ resistor and any load impedance used. Decay time is changed by varying the 1-MΩ resistor.
NOTE
The negative peak detector does require a negative supply voltage! +VCC can be grounded to save dynamic range because the output does not swing above ground
A window detector monitors the input signal to determine if it falls between two voltage levels. Both outputs are true (high) when VREF1 < VIN < VREF2
The comparator outputs A and B are high only when VREF1 < VIN < VREF2, or within the window, where these are defined as:
To determine if the input signal falls outside of the two voltage levels, both inputs on each comparators can be reversed to invert the logic.
The LMV7275 with an open-drain output should be used if the outputs are to be tied together for a common logic output.
Other names for window detectors are: threshold detector, level detector, and amplitude trigger or detector.