SNOSAZ6C August   2008  – November 2015 LMV831 , LMV832 , LMV834

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, 3.3 V
    6. 6.6 Electrical Characteristics, 5 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Characteristics
      2. 7.3.2 EMIRR
      3. 7.3.3 EMIRR Definition
        1. 7.3.3.1 Coupling an RF Signal to the IN+ Pin
        2. 7.3.3.2 Cell Phone Call
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Characteristics
      2. 7.4.2 CMRR Measurement
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics, 3.3 V

Unless otherwise specified, all limits are specified for at TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = V+/2, and RL = 10 kΩ to V+/2.(1)
PARAMETER TEST CONDITIONS MIN(3) TYP(2) MAX(3) UNIT
VOS Input offset voltage(6) TA = 25°C ±0.25 ±1 mV
–40°C ≤ TA ≤ +125°C ±1.23
TCVOS Input offset voltage
temperature drift(6)(7) 		LMV831,
LMV832		 ±0.5 ±1.5 μV/°C
LMV834 ±0.5 ±1.7
IB Input bias current(7) TA = 25°C 0.1 10 pA
–40°C ≤ TA ≤ +125°C 500
IOS Input offset current 1 pA
CMRR Common-mode
rejection ratio(6) 		0.2 V ≤ VCM ≤ V+ – 1.2 V TA = 25°C 76 91 dB
–40°C ≤ TA ≤ +125°C 75
PSRR Power supply
rejection ratio(6) 		2.7 V ≤ V+ ≤ 5.5 V,
VOUT = 1 V		 TA = 25°C 76 93 dB
–40°C ≤ TA ≤ +125°C 75
EMIRR EMI rejection ratio,
IN+ and IN–(5) 		VRF_PEAK = 100 mVP (−20 dBP),
f = 400 MHz		 80 dB
VRF_PEAK = 100 mVP (−20 dBP),
f = 900 MHz		 90
VRF_PEAK = 100 mVP (−20 dBP),
f = 1800 MHz		 110
VRF_PEAK = 100 mVP (−20 dBP),
f = 2400 MHz		 120
CMVR Input common-mode
voltage range		 CMRR ≥ 65 dB −0.1 2.1 V
AVOL Large signal
voltage gain(8) 		RL = 2 kΩ,
VOUT = 0.15 V to 1.65 V,
VOUT = 3.15 V to 1.65 V		 LMV831,
LMV832		 102 121 dB
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C		 102
LMV834 102 121
LMV834
–40°C ≤ TA ≤ +125°C		 102
RL = 10 kΩ,
VOUT = 0.1 V to 1.65 V,
VOUT = 3.2 V to 1.65 V		 LMV831,
LMV832		 104 126
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C		 104
LMV834 104 123
LMV834
–40°C ≤ TA ≤ +125°C		 103
VOUT Output voltage
swing high		 RL = 2 kΩ to V+/2 LMV831,
LMV832		 29 36 mV from either rail
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C		 43
LMV834 31 38
LMV834
–40°C ≤ TA ≤ +125°C		 44
RL = 10 kΩ to V+/2 LMV831,
LMV832		 6 8
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C		 9
LMV834 7 9
LMV834
–40°C ≤ TA ≤ +125°C		 10
Output voltage
swing low		 R = 2 kΩ to V+/2 TA = 25°C 25 34
–40°C ≤ TA ≤ +125°C 43
RL = 10 kΩ to V+/2 TA = 25°C 5 8
–40°C ≤ TA ≤ +125°C 10
IOUT Output short circuit
current		 Sourcing, VOUT = VCM,
VIN = 100 mV		 LMV831,
LMV832		 27 28 mA
LMV831,
LMV832,
–40°C ≤ TA ≤ +125°C		 22
LMV834 24 28
LMV834
–40°C ≤ TA ≤ +125°C		 19
Sinking, VOUT = VCM,
VIN = −100 mV		 TA = 25°C 27 32
–40°C ≤ TA ≤ +125°C 21
IS Supply current LMV831 0.24 0.27 mA
LMV831,
–40°C ≤ TA ≤ +125°C		 0.3
LMV832 0.46 0.51
LMV832,
–40°C ≤ TA ≤ +125°C		 0.58
LMV834 0.9 1
LMV834,
–40°C ≤ TA ≤ +125°C		 1.16
SR Slew rate(4) AV = +1, VOUT = 1 VPP,
10% to 90%		 2 V/μs
GBW Gain bandwidth
product		 3.3 MHz
Φm Phase margin 65 deg
en Input referred
voltage noise		 f = 1 kHz 12 nV/√Hz
f = 10 kHz 10
in Input referred
current noise		 f = 1 kHz 0.005 pA/√Hz
ROUT Closed-loop
output impedance		 f = 2 MHz 500 Ω
CIN Common-mode
input capacitance		 15 pF
Differential-mode
input capacitance		 20
THD+N Total harmonic distortion + noise f = 1 kHz, AV = 1, BW ≥ 500 kHz 0.02%
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ> TA.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(3) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method.
(4) Number specified is the slower of positive and negative slew rates.
(5) The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).
(6) The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting distribution.
(7) This parameter is specified by design and/or characterization and is not tested in production.
(8) The specified limits represent the lower of the measured values for each output range condition.