SNOSAZ6C August   2008  – November 2015 LMV831 , LMV832 , LMV834

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, 3.3 V
    6. 6.6 Electrical Characteristics, 5 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Characteristics
      2. 7.3.2 EMIRR
      3. 7.3.3 EMIRR Definition
        1. 7.3.3.1 Coupling an RF Signal to the IN+ Pin
        2. 7.3.3.2 Cell Phone Call
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Characteristics
      2. 7.4.2 CMRR Measurement
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Output Characteristics

As already mentioned the output is rail-to-rail. When loading the output with a 10-kΩ resistor the maximum swing of the output is typically 6 mV from the positive and negative rail.

The output of the LMV83x can drive currents up to 30 mA at 3.3 V and even up to 65 mA at 5 V.

The LMV83x can be connected as noninverting unity-gain amplifiers. This configuration is the most sensitive to capacitive loading. The combination of a capacitive load placed at the output of an amplifier along with the output impedance of the amplifier creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response will be under damped which causes peaking in the transfer and, when there is too much peaking, the operational amplifier might start oscillating. The LMV83x can directly drive capacitive loads up to 200 pF without any stability issues. In order to drive heavier capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 46. By using this isolation resistor, the capacitive load is isolated from the output of the amplifier, and hence, the pole caused by CL is no longer in the feedback loop. The larger the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive.

LMV831 LMV832 LMV834 30024163.gifFigure 46. Isolating Capacitive Load

A resistor value of around 150 Ω would be sufficient. As an example some values are given in Table 1, for 5 V.

Table 1. Resistor Values

CLOAD RISO
300 pF 165 Ω
400 pF 175 Ω
500 pF 185 Ω