BIAS01 |
20 |
BYP |
If not using the multiplier, this
pin can be left open. If using the multiplier, bypass this pin to
GND with a 10-nF capacitor for optimal noise performance. |
BIAS23 |
31 |
BYP |
If not using the multiplier, this
pin can be left open. If using the multiplier, bypass this pin to
GND with a 10-µF and 0.1-µF capacitor for optimal noise performance. |
CLKIN_N |
7 |
I |
Differential reference
input clock. Internal 50-Ω termination. AC-couple with a capacitor
appropriate to the input frequency (typically 0.1 µF or smaller). If
using single-ended, terminate unused side with a series AC-coupling
capacitor 50-Ω resistor to GND. |
CLKIN_P |
6 |
CLKOUT0_N |
15 |
O |
Differential clock
output pairs. Each pin is an open-collector output with internally
integrated 50-Ω resistor with programmable output swing. AC
coupling required. |
CLKOUT0_P |
14 |
CLKOUT1_N |
19 |
CLKOUT1_P |
18 |
CLKOUT2_N |
32 |
CLKOUT2_P |
33 |
CLKOUT3_N |
36 |
CLKOUT3_P |
37 |
CS# |
10 |
I |
SPI chip select. High impedance CMOS
input. Accepts up to 3.3 V. |
DAP |
DAP |
GND |
Ground these
pins. |
GND |
5,13,17,26,34,38 |
LOGICLKOUT_N |
27 |
O |
Differential clock
output pair. Selectable CML, LVDS, or LVPECL format. Programmable
common-mode voltage. |
LOGICLKOUT_P |
28 |
LOGISYSREFOUT_N |
23 |
O |
Differential clock
output pair. Selectable CML, LVDS, or LVPECL format. Programmable
common-mode voltage. |
LOGISYSREFOUT_P |
24 |
MUXOUT |
1 |
O |
Multiplexed pin serial data readback
and lock status of the multiplier. |
SCK |
8 |
I |
SPI clock. High impedance CMOS
input. Accepts up to 3.3 V. |
SDI |
9 |
I |
SPI data input. High impedance CMOS
input. Accepts up to 3.3 V. |
SYSREFREQ_N |
3 |
I |
Differential SYSREF
request input for JESD204B support. Internal 50-Ω AC coupled to
internal common-mode voltage or capacitor to GND. Supports AC and DC
coupling which can directly accept a common mode voltage of 1.2 to 2
V. |
SYSREFREQ_P |
2 |
SYSREFOUT0_N |
12 |
O |
Differential SYSREF CML
output pairs for JESD204B support. Supports AC and DC coupling with
programmable common-mode voltage of 0.6 to 2 volts. |
SYSREFOUT0_P |
11 |
SYSREFOUT1_N |
22 |
SYSREFOUT1_P |
21 |
SYSREFOUT2_N |
29 |
SYSREFOUT2_P |
30 |
SYSREFOUT3_N |
39 |
SYSREFOUT3_P |
40 |
VCC_CLKIN |
4 |
PWR |
Connect to a 2.5-V
supply. Recommend a shunt high frequency capacitor (typically 0.1 µF
or smaller) close to the pin in parallel with larger capacitors
(typically 1 µF and 10 µF) farther away. |
VCC_LOGICLK |
25 |
VCC01 |
16 |
VCC23 |
35 |