SNAS800B July 2021 – February 2024 LMX1204
PRODUCTION DATA
The SYSREF circuitry can produce an output signal that is synchronized to fCLKIN. This output can be a single pulse, series of pulses, or a continuous stream of pulses. In generator mode, the SYSREF_DIV_PRE and SYSREF_DIV values are used to divide the CLKIN frequency to a lower frequency that is reclocked to the output. In repeater mode, this signal is instead input at the SYSREFREQ pins. For each of the outputs, there is an independent delay control.
SYSREF_MODE | DESCRIPTION |
---|---|
0 | Generator Mode (Continuous) Internal generator creates a continuous stream of SYSREF pulses. The SYSREFREQ pins or the SYSREFREQ_SPI field can be used to gate the SYSREF divider from the channels for improved noise isolation without disrupting the synchronization of the SYSREF dividers. The SYSREFREQ pins or the SYSREFREQ_SPI field must be high for a SYSREF output to come out. |
1 | Generator Mode (Pulser) Internal generator generates a burst of 1 - 16 pulses that is set by SYSREF_PULSE_COUNT that occurs after a rising edge on the SYSREFREQ pins |
2 | Repeater Mode SYSREFREQ pins are reclocked to clock outputs and then delayed in accordance to the SYSREF_DELAY_BYPASS field before being sent to the SYSREFOUT outputs. |
For the frequency of the SYSREF output in generator mode, the SYSREF_DIV_PRE divider is necessary to verify that the input of the SYSREF_DIV divider is not more than 3.2 GHz.
fCLKIN | SYSREF_DIV_PRE | TOTAL SYSREF DIVIDE RANGE |
---|---|---|
3.2 GHz or Less | ÷1, 2, or 4 | ÷2,3,4,...16380 |
3.2 GHz < fCLKIN ≤ 6.4 GHz | ÷2 or 4 | ÷4,6,8, … 16380 |
fCLKIN > 6.4 GHz | ÷4 | ÷8,12,16, … 16380 |
For the delay, the input clock frequency is divided by SYSREF_DELAY_DIV to generate fINTERPOLATOR. This has a restricted range as shown in Table 6-13. Note also that when SYSREF_DELAY_BYPASS=0 or 2 (delaygen engaged for generator mode), and SYSREF_MODE = 0 or 1 (a generator mode) the SYSREF output frequency must be a multiple of the phase interpolator frequency.
fINTERPOLATOR % fSYSREF = 0.
fCLKIN | SYSREF_DELAY_DIV | SYSREFx_DELAY_SCALE | fINTERPOLATOR |
---|---|---|---|
6.4 GHz < fCLKIN ≤ 12.8GHz | 16 | 0 | 0.4 to 0.8 GHz |
3.2 GHz < fCLKIN ≤ 6.4 GHz | 8 | 0 | 0.4 to 0.8 GHz |
1.6 GHz < fCLKIN ≤ 3.2 GHz | 4 | 0 | 0.4 to 0.8 GHz |
0.8 GHz < fCLKIN ≤1.6 GHz | 2 | 0 | 0.4 to 0.8 GHz |
0.4 GHz < fCLKIN ≤ 0.8 GHz | 2 | 1 | 0.2 to 0.4 GHz |
0.3 GHz < fCLKIN ≤ 0.4 GHz | 2 | 2 | 0.15 to 0.2 GHz |
The maximum delay is equal to the phase interpolator period and there are 4x127 = 508 different delay steps. Use Equation 2 to calculate the size of each step.
Use Equation 3 to calculate the total delay.
Table 6-14 shows the number of steps for each delay.
SYSREFx_DELAY_PHASE | STEPNUMBER |
---|---|
3 | 127 - SYSREFx_DELAY_I |
2 | 254 - SYSREFx_DELAY_Q |
0 | 381 - SYSREFx_DELAY_I |
1 | 508 - SYSREFx_DELAY_Q |
The SYSREF_DELAY_BYPASS field selects between the delay generator output and the repeater mode bypass signal. When SYSREF_MODE is set to continuous or pulser mode, TI recommends to set SYSREF_DELAY_BYPASS to generator mode. If SYSREF_MODE is set to repeater mode, TI recommends to set SYSREF_DELAY_BYPASS to bypass mode.