SNAS800B July   2021  – February 2024 LMX1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier and Filter Modes
          1. 6.3.3.4.1 General Information About the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Using the x1 Clock Multiplier as a Filter
          5. 6.3.3.4.5 Lock Detect for the Clock Multiplier
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_SPI Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
      7. 6.3.7 SYNC Feature
    4. 6.4 Device Functional Modes
  8. 7 Register Map
    1. 7.1 LMX1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SYSREFREQ Input Configuration
      2. 8.1.2 Reducing SYSREF Common Mode Voltages
      3. 8.1.3 Current Consumption
      4. 8.1.4 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)

SYSREF repeater mode with delay enabled is possible with LMX to LMX fanout devices by retiming the SYSREFout at different edge of IQ gen. This retiming can have the delay margin between CLKIN and SYSREFREQ inputs based on SYSREF_DELAY_DIV value.

Table 6-17 shows how the total delay margin for the SYSREF windowing relates the various SYSREF settings.

Table 6-17 SYSREF Phase Adjust Settings for Retime in Repeater Mode
SYSREF_DELAY_DIV POSITION CODE SELECTED DURING SYNC EDGE FOR MAX MARGIN TOTAL MARGIN IN CLKIN CYCLE SYSREFx_DELAY_PHASE SYSREFx_DELAY_Q SYSREFx_DELAY_I

/2

Before 1st edge

I

-1, +1

"11"

0

127

After 1st edge

Qz

-1, +1

"01"

127

0

After 2nd edge

Iz

-1, +1

"00"

0

127

/4

Before 1st edge

Qz

-2, +2

"01"

127

0

After 1st edge

Iz

-2, +2

"00"

0

127

After 2nd edge

Q

-2, +2

"10"

127

0

/8

Before 1st edge

Qz

-5, +3

"01"

127

0

After 1st edge

Qz

-4, +4

"01"

127

0

After 2nd edge

Qz

-3, +5

"01"

127

0

/16

Before 1st edge

I

-9, +7

"11"

0

127

After 1st edge

I

-8, +8

"11"

0

127

After 2nd edge

I

-7, +9

"11"

0

127

Repeater retime mode is required to perform the SYSREF windowing in the initial phase to synchronize the SYSREF_DELAY_DIV in multiple devices. The user can later choose the SYSREFx_DELAY_PHASE, SYSREF_DELAY_Q and SYSREFx_DELAY_I settings for the selected edge for the SYNC.

GUID-20230821-SS0I-MD6L-G8ST-Q5R6RXJS53LC-low.svg Figure 6-11 SYSREF Windowing to Select the Edge Position for SYNC

This configuration must set the device in SYSREF_MODE R17[1:0] value "2" (Repeater mode) and SYSREF_DELAY_BYPASS R72[1:0] value "2" (Delay gen engaged in all modes).

For Glitch Free Output

  • Keep the same state for the SYSREFREQ pin when switching from request mode to windowing mode and back to request mode. For example, if the SYSREFREQ pin is high (or low) when windowing mode starts, make sure the pin state is high (or low) again after windowing mode ends before programing CLKPOS_CAPTURE_EN.
  • The SYSREFREQ pin must be set low when switching from or to SYNC mode.

Other Pointers With SYSREF Windowing

  • The SYSREFREQ pins need to be held high for a minimum time of 3/fCLKIN + 1.6ns and only after this time rb_CLKPOS field is valid.
  • If the user infers multiple valid SYSREFREQ_DELAY_STEP values from rb_CLKPOS registers to avoid setup-hold violations, choosing the lowest valid SYSREFREQ_DELAY_STEP is recommended to minimize variation over temperature.

If Using SYNC Feature

  • Only one SYSREFREQ pin rising edge is permitted per 75 input clock cycles
  • SYSREFREQ has to stay high for >6 clock cycles