SNAS850 December 2024 LMX1205
ADVANCE INFORMATION
Set the CLK_MUX to Divided to a divide value by 2, 3, 4, 5, 6, 7, or 8. This is set by the CLK_DIV word. When using the clock divider, any change to the input frequency requires the CLK_DIV_RST bit to be toggled from 1 to 0.
CLK_DIV | DIVIDE | DUTY CYCLE |
---|---|---|
0 | Reserved | n/a |
1 | 2 | 50% |
2 | 3 | 33% |
3 | 4 | 50% |
4 | 5 | 40% |
5 | 6 | 50% |
6 | 7 | 43% |
7 | 8 | 50% |