The SYSREFREQ pins must be held
high for a minimum time of 3/fCLKIN + 1.6ns and only after this time
rb_CLKPOS field is valid.
If the user infers multiple valid
SYSREFREQ_DLY values from rb_CLKPOS registers to avoid setup and hold time
violations. TI recommends to choose the lowest valid SYSREFREQ_DLY to minimize
variation over temperature.
The programmed SYSREFREQ_DLY for
optimized setup and hold time after SYSREF windowing adjusts the internal
SYSREFREQ, but the SYSREFREQ_DLY does not show the movement in SYSREF windowing
readback code. SYSREF windowing always evaluates the signals at the pins.