SNAS850 December   2024 LMX1205

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Input
        1. 6.3.3.1 Clock Input Adjustable Delay
      4. 6.3.4 Clock Outputs
        1. 6.3.4.1 Clock Output Buffers
        2. 6.3.4.2 Clock Output Adjustable Delay
        3. 6.3.4.3 Clock MUX
        4. 6.3.4.4 Clock Divider
        5. 6.3.4.5 Clock Multiplier
          1. 6.3.4.5.1 General Information About the Clock Multiplier
          2. 6.3.4.5.2 State Machine Clock for the Clock Multiplier
            1. 6.3.4.5.2.1 State Machine Clock
          3. 6.3.4.5.3 Calibration for the Clock Multiplier
          4. 6.3.4.5.4 Lock Detect for the Clock Multiplier
      5. 6.3.5 LOGICLK Outputs
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 LOGISYSREF Output Buffer
          3. 6.3.6.1.3 SYSREF Frequency and Delay Generation
          4. 6.3.6.1.4 SYSREFREQ Pins and SYSREFREQ SPI Controlled Fields
            1. 6.3.6.1.4.1 SYSREFREQ Pins Common-Mode Voltage
            2. 6.3.6.1.4.2 SYSREFREQ Windowing Feature
              1. 6.3.6.1.4.2.1 General Procedure Flowchart for SYSREF Windowing Operation
              2. 6.3.6.1.4.2.2 Other Guidance For SYSREF Windowing
              3. 6.3.6.1.4.2.3 For Glitch-Free Output
              4. 6.3.6.1.4.2.4 If Using SYNC Feature
              5. 6.3.6.1.4.2.5 SYNC Feature
      7. 6.3.7 Power-Up Timing
      8. 6.3.8 Treatment of Unused Pins
    4. 6.4 Device Functional Modes Configurations
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Reference
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
        3. 8.1.1.3 Application Plots
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.3.6.1.3 SYSREF Frequency and Delay Generation

For the frequency of the SYSREF output in generator mode, the SYSREF_DIV_PRE divider is necessary to verify that the input of the SYSREF_DIV divider is not more than 3.2GHz.

Table 6-11 SYSREF_DIV_PRE Setup
fCLKIN SYSREF_DIV_PRE TOTAL SYSREF DIVIDE RANGE
3.2GHz or Less ÷1, 2, or 4 ÷2, 3, 4, ...16380
3.2GHz < fCLKIN ≤ 6.4GHz ÷2 or 4 ÷4, 6, 8, … 16380
fCLKIN > 6.4GHz ÷4 ÷8, 12, 16, … 16380

For the delay, the input clock frequency is divided by SYSREF_DLY_DIV to generate fINTERPOLATOR. This has a restricted range as shown in Table 6-12. Note also that when SYSREF_DLY_BYP = 1 (delaygen engaged) and SYSREF_MODE = 0 or 1 (a generator mode) the SYSREF output frequency must be a multiple of the phase interpolator frequency.

fINTERPOLATOR % fSYSREF = 0.

Table 6-12 SYSREF Delay Setup
fCLKIN SYSREF_DLY_DIV SYSREF_DLY_SCALE fINTERPOLATOR
6.4GHz < fCLKIN ≤ 12.8GHz 16 0 0.4GHz to 0.8GHz
3.2GHz < fCLKIN ≤ 6.4GHz 8 0 0.4GHz to 0.8GHz
1.6GHz < fCLKIN ≤ 3.2GHz 4 0 0.4GHz to 0.8GHz
0.8GHz < fCLKIN ≤ 1.6GHz 2 0 0.4GHz to 0.8GHz
0.4GHz < fCLKIN ≤ 0.8GHz 2 1 0.2GHz to 0.4GHz
0.3GHz < fCLKIN ≤ 0.4GHz 2 2 0.15GHz to 0.2GHz

The maximum delay is equal to the phase interpolator period and there are 4 × 127 = 508 different delay steps. Use Equation 2 to calculate the size of each step.

Equation 2. DelayStepSize = 1 / ( fINTERPOLATOR × 508) = SYSREF_DLY_DIV / ( fCLKIN × 508)

Use Equation 3 to calculate the total delay.

Equation 3. TotalDelay = DelayStepSize × StepNumber

Table 6-13 shows the number of steps for each delay.

Below table can be used to program the desired delay step number.
Table 6-13 Calculation of StepNumber
Step Number Range SYSREFx_DLY_PHASE SYSREFx_DLY
0 - 127 (127 - SYSREFx_DLY) 0 127 to 0
127 - 254 (127 + SYSREFx_DLY) 1 0 to 127
254 - 381 (381 - SYSREFx_DLY) 3 127 to 0
381 - 508 (381 + SYSREFx_DLY) 2 0 to 127

The SYSREF_DLY_BYP field selects the delay path in SYSREF generation output and repeater retime mode.

Below table shows the unusable step number for the SYSREF delay in different SYSREF_MODE and SYSREF dividers settings.
Table 6-14 SYSREF Delay Unusable Step Numbers
SYSREF_MODE SYSREF_DIV_PRE SYSREF_DIV SYSREF_DLY_DIV Unusable Step Number
Continuous Or Pulsed 1 2 or 3 2 Invalid Combination
4
8
16
2 2 15 to 45
4 Invalid Combination
8
16
4 2 10 to 45
4 140 to 175
8 Invalid Combination
16
1 >= 4 2 10 to 45
4 390 to 430
8 215 to 240
16 Invalid Combination
2 2 265 to 300
4
8 390 to 430
16 280 to 300
4 2 265 to 300
4
8 140 to 175
16 390 to 430
Repeater Retime x x 2 20 to 50
4 145 to 180
8 85 to 125
16 120 to 160

Figure shows an example of unusable delay step positions, where SYSREF rising edge lies around the phase interpolator rising edge.

LMX1205 Unusable Delay Step Numbers Figure 6-9 Unusable Delay Step Numbers

Table shows the SYSREF output delay step size and it varies with the phase interpolator frequency.

LMX1205 SYSREF Delay Step Size Figure 6-10 SYSREF Delay Step Size