SNAS850
December 2024
LMX1205
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Timing Diagram
5.8
Typical Characteristics
6
Detailed Description
6.1
Overview
6.1.1
Range of Dividers and Multiplier
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Power On Reset
6.3.2
Temperature Sensor
6.3.3
Clock Input
6.3.3.1
Clock Input Adjustable Delay
6.3.4
Clock Outputs
6.3.4.1
Clock Output Buffers
6.3.4.2
Clock Output Adjustable Delay
6.3.4.3
Clock MUX
6.3.4.4
Clock Divider
6.3.4.5
Clock Multiplier
6.3.4.5.1
General Information About the Clock Multiplier
6.3.4.5.2
State Machine Clock for the Clock Multiplier
6.3.4.5.2.1
State Machine Clock
6.3.4.5.3
Calibration for the Clock Multiplier
6.3.4.5.4
Lock Detect for the Clock Multiplier
6.3.5
LOGICLK Outputs
6.3.5.1
LOGICLK Output Format
6.3.5.2
LOGICLK Dividers
6.3.6
SYSREF
6.3.6.1
SYSREF Output Buffers
6.3.6.1.1
SYSREF Output Buffers for Main Clocks (SYSREFOUT)
6.3.6.1.2
LOGISYSREF Output Buffer
6.3.6.1.3
SYSREF Frequency and Delay Generation
6.3.6.1.4
SYSREFREQ Pins and SYSREFREQ SPI Controlled Fields
6.3.6.1.4.1
SYSREFREQ Pins Common-Mode Voltage
6.3.6.1.4.2
SYSREFREQ Windowing Feature
6.3.6.1.4.2.1
General Procedure Flowchart for SYSREF Windowing Operation
6.3.6.1.4.2.2
Other Guidance For SYSREF Windowing
6.3.6.1.4.2.3
For Glitch-Free Output
6.3.6.1.4.2.4
If Using SYNC Feature
6.3.6.1.4.2.5
SYNC Feature
6.3.7
Power-Up Timing
6.3.8
Treatment of Unused Pins
6.4
Device Functional Modes Configurations
7
Register Map
7.1
Device Registers
8
Application and Implementation
8.1
Reference
8.1.1
Typical Application
8.1.1.1
Design Requirements
8.1.1.2
Detailed Design Procedure
8.1.1.3
Application Plots
8.2
Power Supply Recommendations
8.3
Layout
8.3.1
Layout Guidelines
8.3.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.2
Documentation Support
9.2.1
Related Documentation
9.3
Receiving Notification of Documentation Updates
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHA|40
MPQF135D
Thermal pad, mechanical data (Package|Pins)
RHA|40
QFND650
Orderable Information
snas850_oa
1
Features
Output frequency: 300MHz to 12.8GHz
Noiseless adjustable input delay up to 60ps with 1.1ps resolution
Individual adjustable output delays up to 55ps with 0.9ps resolution
Ultra-low noise
Noise floor: –159dBc/Hz at 6GHz output
Additive jitter (DC to f
CLK
): 36fs
Additive jitter (100Hz to 100MHz): 10fs
Four high-frequency clocks with corresponding SYSREF outputs
Shared divide by 1 (Bypass), 2, 3, 4, 5, 6, 7, and 8
Shared programmable multiplier x2, x3, x4, x5, x6, x7 and x8
LOGICLK output with corresponding SYSREF output
On separate divide bank
1, 2, 4 pre-divider
1 (bypass), 2, …, 1023 post divider
Second logic clock option with additional divider 1, 2, 4 & 8
Six programmable output power levels
Synchronized SYSREF clock outputs
508 delay step adjustments of less than 2.5ps at 12.8GHz
Generator, repeater and repeater retime modes
Windowing feature for SYSREFREQ pins to optimize timing
SYNC feature to all divides and multiple devices
Operating voltage: 2.5V
Operating temperature: –40ºC to +85ºC