SNAS850 December 2024 LMX1205
ADVANCE INFORMATION
When the device is powered up, the power on reset (POR) resets all registers to a default state as well as resets all state machines and dividers. For the power on reset state, all SYSREF outputs are disabled and all the dividers are bypassed; the device functions as a 4-output buffer. Users must wait 100µs after the power supply rails before programming other registers to verify that the RESET is finished. If the power on reset happens when there is no device clock present, the device functions properly, however, the current changes once an input clock is presented.
\Performing a software power on reset by writing RESET=1 in the SPI bus is both possible and generally good practice. The RESET bit self-clears once any other register is written to. The SPI bus can be used to override these states to the desired settings.
Although the device does have an automatic power on reset, the device can be impacted by different ramp rates on the different supply pins, especially in the presence of a strong input clock signal. Performing a software reset after POR is recommended. This reset can be done by programming RESET=1. The reset bit can be cleared by programming any other register or setting RESET back to zero. Even at maximum allowed SPI bus speed, the software reset event always completes before the subsequent SPI write.