SNAS850 December 2024 LMX1205
ADVANCE INFORMATION
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Current Consumption | |||||||
ICC | Supply Current (1) | Powered up, all Clock outputs and SYSREFs on | 1130 | mA | |||
Powered up, all Clock outputs on, all SYSREF off | 700 | ||||||
Powered up, all Clock outputs and SYSREF off | 370 | ||||||
Powered down | 13.5 | ||||||
IADD | Additive output current | OUTx_PWR = 6 | 64 | mA | |||
Multiplier current | Divide, CLK_DIV = 8 | 60 | |||||
Multiplier, CLK_MULT = x8 | 360 | ||||||
SYSREF current | Running at 100MHz Generation mode, all outputs on |
425 | |||||
LOGICLK current | LOGICLK enabled with LOGISYSREF | 85 | |||||
SYSREF | |||||||
fSYSREF | SYSREF output frequency | Generator mode | Generator mode | 200 | MHz | ||
fSYSREF | SYSREF output frequency | Repeater mode | Repeater mode | 100 | MHz | ||
TSYNC | Pulse width required for SYNC signal | Tsync = 6xT of fCLKIN , fCLKIN = 6GHz | 1000 | ps | |||
Δt | SYSREF delay step size | Δt = SYSREF_DLY_DIV/ (508 x fCLKIN), fCLKIN = 12.8GHz | 3 | ps | |||
tRISE | Rise time (20% to 80%) | SYSREFOUT | 45 | ps | |||
LOGISYSREFOUT | CML | 65 | ps | ||||
LVDS | 120 | 175 | ps | ||||
tFALL | Fall time (20% to 80%) | SYSREFOUT | 45 | ps | |||
LOGISYSREFOUT | CML | 65 | ps | ||||
LVDS | 120 | 175 | ps | ||||
VODDIFF | Differential pk-pk output voltage | SYSREFOUT, SYSREFx_PWR = 4, SYSREFx_VCM = 10 | 0.9 | Vpp | |||
LOGISYSREFOUT | CML | 0.9 | Vpp | ||||
LVDS | 0.7 | Vpp | |||||
VSYSREFCM | Common mode voltage | SYSREFOUT | CML SYSREFx_VCM=41, 100Ω Differential Load |
1.35 | 1.5 | 1.65 | V |
CML SYSREFx_VCM=4, 100Ω Differential Load |
0.45 | 0.5 | 0.55 | V | |||
LOGISYSREFOUT | LVDS 100Ω Differential Load |
0.75 | 1.4 | V | |||
SYSREFREQ Pins | |||||||
VSYSREFIN | Differential pk-pk Voltage input range | AC differential voltage | 0.8 | 2 | Vpp | ||
VSYSREFIN | Single-ended voltage input range | AC Coupled to SYSREFREQ_P; SYSREFREQ_N AC coupled to GND |
AC Coupled to SYSREFREQ_P; SYSREFREQ_N AC coupled to GND |
0.6 | 1.7 | Vpp | |
VCM | Input common mode voltage | Differential 100Ω Termination, DC coupled Set externally |
1.2 | 1.3 | 2 | V | |
Clock Input | |||||||
fIN | Input frequency | 0.3 | 12.8 | GHz | |||
PIN | Input power | Single-ended power at CLKIN_P or CLKIN_N | 0 | 10 | dBm | ||
ϕIN | Input delay range | 60 | ps | ||||
ΔIN | Input delay programmable step | 1.1 | ps | ||||
Clock Outputs | |||||||
fOUT | Output frequency | Divide-by-2 | 0.15 | 6.4 | GHz | ||
fOUT | Output frequency | Buffer Mode | 0.3 | 12.8 | |||
fOUT | Output frequency | Multiplier Mode | 6.4 | 12.8 | |||
fOUT | Output frequency | LOGICLK output | 1 | 800 | MHz | ||
tCAL | Calibration-time | Multiplier calibration time | fIN = 6.4GHz; x2 fSMCLK = 28 MHz |
750 | µs | ||
pOUT | Output power | Single-Ended | fCLKLOUT= 6GHz OUTx_PWR = 6 |
4.8 | dBm | ||
tRISE | Rise time (20% to 80%) | fCLKOUT = 300 MHz | 45 | ps | |||
tFALL | Fall time (20% to 80%) | fCLKOUT = 300 MHz | 45 | ps | |||
VLOGICLKCM | Common mode voltage | LOGICLKOUT0 | LVDS | 0.7 | 1.2 | 1.5 | V |
ϕIN | Output delay range | 55 | ps | ||||
ΔϕIN | Output delay programmable step size | 0.9 | ps | ||||
Propagation Delay and Skew | |||||||
| tSKEW | | Magnitude of skew between outputs | CLKOUTx to CLKOUTy, not LOGICLK | 1 | 10 | ps | ||
| tSKEW | | Magnitude of skew between CLKOUT and SYSREF | SYSREF Continuous/Pulse Mode | SYSREF delay gen bypass | 60 | ps | ||
| tSKEW | | Magnitude of skew between CLKOUT and SYSREF | SYSREF Repeater retime Mode | SYSREF delay gen bypass | 100 | ps | ||
ΔtDLY/ΔT | Propagation delay variation over temperature | Buffer mode | 0.02 | 0.06 | 0.10 | ps/℃ | |
tDLY | Propagation delay | Buffer mode | TA = 25℃ | 165 | ps | ||
Divider Mode | 175 | ps | |||||
Multiplier Mode | 155 | ps | |||||
tDLY | Propagation delay | SYSREF out Repeater mode | TA = 25℃ | 185 | ps | ||
Noise, Jitter, and Spurs | |||||||
σCLKOUT | CLKOUT Additive jitter | Additive Jitter. 100Hz to 100MHz integration bandwidth. | Buffer Mode | 10 | fs, rms | ||
x2 Multiplier | 21 | ||||||
x3 Multiplier | 25 | ||||||
x4 Multiplier | 33 | ||||||
x5 Multiplier | 35 | ||||||
x6 Multiplier | 48 | ||||||
x7 Multiplier | 50 | ||||||
x8 Multiplier | 60 | ||||||
1/fCLKOUT | 1/f flicker noise | Slew Rate > 8 V/ns, fCLK=6GHz | Buffer Mode | –154 | dBc/Hz | ||
NFCLKOUT | Noise Floor | fOUT = 6.4GHz; fOffset =100MHz | Buffer Mode | –159 | dBc/Hz | ||
Divide-by-2 | –158.5 | ||||||
Multiplier (x2,x3,x4,x5,x6,x7,x8) | –159.5 | ||||||
NFLOGICLK | Noise Floor | LOGICLK output, 300 MHz | CML | –150.5 | dBc/Hz | ||
LVDS | –151.5 | ||||||
H2 | Second harmonic | Buffer Mode fOUT=6.4GHz |
Differential | –25 | dBc | ||
Single-Ended | –15 | ||||||
Divide by 2 fOUT=6.4GHz |
Single-Ended | –17 | |||||
H1/M | Input clock leakage spur | fOUT = 12GHz (differential) | x2 (fSPUR = 6GHz) | –40 | dBc | ||
fOUT = 12GHz (differential) | x3 (fSPUR = 4GHz) | –40 | |||||
fOUT = 12GHz (differential) | x4 (fSPUR = 3GHz) | –50 | |||||
fOUT = 12GHz (differential) | x6 (fSPUR = 2GHz) | -50 | |||||
fOUT = 10GHz (differential) | x5 (fSPUR = 2GHz) | -50 | |||||
fOUT = 10.5GHz (differential) | x7 (fSPUR = 1.5GHz) | -52 | |||||
fOUT = 12GHz (differential) | x8 (fSPUR = 1.5GHz) | -55 | |||||
Pcrosstalk | LOGICLK to CLKOUT | fSPUR = 300MHz (differential) | –70 | dBc | |||
SYSREFOUT to CLKOUT | Generation mode | -70 | dBc | ||||
repeater mode | -65 | dBc | |||||
PLEAK | CLKIN to CLKOUT Leakage in Buffer Mode | Differential Input | -70 | dBc | |||
Digital Interface (SCK, SDI, CS#, MUXOUT) | |||||||
VIH | High-level input voltage | SCK, SDI, CS# | 1.4 | 3.3 | V | ||
VIL | Low-level input voltage | 0 | 0.4 | ||||
VOH | High-level output voltage | IOH = 5mA | 1.4 | Vcc | |||
IOH = 0.1mA | 2.2 | Vcc | |||||
VOL | Low-level output voltage | IOL = 5mA | 0.45 | ||||
IIH | High-level input current | –42 | 42 | μA | |||
IIL | Low-level input current | –25 | 25 |