SNAS866 December   2023 LMX1214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power-On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
      4. 6.3.4 AUXCLK Output
        1. 6.3.4.1 AUXCLKOUT Output Format
        2. 6.3.4.2 AUXCLK_DIV_PRE and AUXCLK_DIV Dividers
      5. 6.3.5 SYNC Input Pins
        1. 6.3.5.1 SYNC Pins Common-Mode Voltage
        2. 6.3.5.2 Windowing Feature
    4. 6.4 Device Functional Modes Configurations
      1. 6.4.1 Pin Mode Control
  8. 7 Application and Implementation
    1. 7.1 Applications Information
      1. 7.1.1 SYNC Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Register Map

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 POWERDOWN 0 0
R2 0 0 0 0 0 0 1 0 0 0 SMCLK_EN 0 0 0 1 1
R3 CLKOUT3_EN CLKOUT2_EN CLKOUT1_EN CLKOUT0_EN 1 1 1 1 1 0 0 0 0 1 1 0
R4 0 0 CLKOUT1_PWR CLKOUT0_PWR 1 1 1 1 1 1 1 1
R5 0 0 1 1 0 1 1 0 1 1 CLKOUT3_PWR CLKOUT2_PWR
R7 0 1 0 AUXCLKOUT_VCM 1 0 AUXCLK_DIV_PWR_PRE 0 1 1 AUXCLKOUT_PWR 1
R8 0 0 0 0 0 0 0 AUXCLK_DIV_PRE AUXCLKOUT_EN 0 0 0 AUXCLKOUT_FMT
R9 SYNC_VCM SYNC_EN 0 AUXCLK_DIV_BYP 0 AUXCLK_DIV
R11 rb_CLKPOS
R12 rb_CLKPOS[31:16]
R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNC_DLY_STEP
R14 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKPOS_CAPTURE_EN 1 SYNC_LATCH
R15 0 0 0 0 1 0 1 1 0 SYNC_DLY SYNC_CLR
R23 TS_EN 1 MUXOUT_EN 0 0 0 0 0 0 0 0 0 0 0 0 0
R24 0 0 0 0 rb_TS TS_CNT_EN
R25 0 0 0 0 0 0 1 0 0 CLK_DIV_RST CLK_DIV CLK_MUX
R75 rb_CLKOUT2_EN rb_CLKOUT1_EN rb_CLKOUT0_EN rb_MUXSEL1 0 0 0 0 0 rb_DIVSEL1 rb_DIVSEL0 rb_CE 0 1 1 0
R79 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
R86 0 0 0 0 0 0 0 0 0 0 0 0 0 MUXOUT_EN_OVRD 0 0
R90 0 0 0 0 0 0 0 0 0 AUXCLK_DIV_BYP3 AUXCLK_DIV_BYP2 0 0 0 0 0
Programming is NOT required for buffer mode, but can be done to enable other features and enhancements
Registers Enhancements
R0, R3, R4, and R5 Outputs
R2, R75 Pin Modes
R7,R8,,R9,R79,R90 AUXCLK. R79 and R90 are only needed if using a divide by 1 if bypassing the pre-divider for the AUXCLK
R11,R12,R13,R14,R15 SYNC
R23, R24, R86 MUXOUT, Readback, and Temp Sensor
R25 Main Divide