SNAS883
June 2024
LMX1860-SEP
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Timing Diagram
5.8
Typical Characteristics
6
Detailed Description
6.1
Overview
6.1.1
Range of Dividers and Multiplier
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Power On Reset
6.3.2
Temperature Sensor
6.3.3
Clock Outputs
6.3.3.1
Clock Output Buffers
6.3.3.2
Clock MUX
6.3.3.3
Clock Divider
6.3.3.4
Clock Multiplier
6.3.3.4.1
General Information about the Clock Multiplier
6.3.3.4.2
State Machine Clock for the Clock Multiplier
6.3.3.4.2.1
State Machine Clock
6.3.3.4.3
Calibration for the Clock Multiplier
6.3.3.4.4
Lock Detect for the Clock Multiplier
6.3.3.4.5
Watchdog Timer
6.3.4
Device Functional Modes Configurations
6.3.5
LOGICLK Output
6.3.5.1
LOGICLK Output Format
6.3.5.2
LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
6.3.6
SYSREF
6.3.6.1
SYSREF Output Buffers
6.3.6.1.1
SYSREF Output Buffers for Main Clocks (SYSREFOUT)
6.3.6.1.2
SYSREF Output Buffer for LOGICLK
6.3.6.2
SYSREF Frequency and Delay Generation
6.3.6.3
SYSREFREQ Pins and SYSREFREQ_FORCE Field
6.3.6.3.1
SYSREFREQ Pins Common-Mode Voltage
6.3.6.3.2
SYSREFREQ Windowing Feature
6.3.6.3.2.1
General Procedure Flowchart for SYSREF Windowing Operation
6.3.6.3.2.2
SYSREFREQ Repeater Mode With Delay Generation (Retime)
6.3.6.3.2.3
Other Guidance For SYSREF Windowing
6.3.6.3.2.4
For Glitch-Free Output
6.3.6.3.2.5
If Using SYNC Feature
6.3.6.3.3
SYNC Feature
6.3.7
Pin Mode Control
6.3.7.1
Chip Enable (CE)
6.3.7.2
Output Channel Control
6.3.7.3
Logic Output Control
6.3.7.4
SYSREF Output Control
6.3.7.5
Device Mode Selection
6.3.7.6
Divider or Multiplier Value Selection
6.3.7.7
Calibration Control Pin
6.3.7.8
Output Power Control
7
Application and Implementation
7.1
Application Information
7.1.1
SYSREFREQ Input Configuration
7.1.2
Treatment of Unused Pins
7.1.3
Current Consumption
7.2
Typical Applications
7.2.1
Local Oscillator Distribution Application
7.2.1.1
Design Requirements
7.2.1.2
Detailed Design Procedure
7.2.1.3
Application Plot
7.2.2
JESD204B/C Clock Distribution Application
7.3
Layout
7.3.1
Layout Guidelines
7.3.2
Layout Example
7.4
Power Supply Recommendations
7.4.1
Power-Up Timing
7.5
Register Map
7.5.1
Device Registers
8
Device and Documentation Support
8.1
Device Support
8.2
Documentation Support
8.2.1
Related Documentation
8.3
Receiving Notification of Documentation Updates
8.4
Support Resources
8.5
Trademarks
8.6
Electrostatic Discharge Caution
8.7
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PAP|64
MPQF071C
Thermal pad, mechanical data (Package|Pins)
PAP|64
PPTD060M
Orderable Information
snas883_oa
snas883_pm
1
Features
VID #V62/24630
Total ionizing dose 30krad (ELDRS-free)
Single event latch-up (SEL) immune up to 43MeV - cm
2
/mg
Single event functional interrupt (SEFI) immune up to 43MeV - cm
2
/mg
Clock buffer for 300MHz to 15GHz frequency
Ultra-Low Noise
Noise floor of –159dBc/Hz at 6GHz output
36-fs additive jitter (100Hz to f
CLK
) at 6GHz output
5fs additive jitter (100Hz - 100MHz)
4 high-frequency clocks with corresponding SYSREF outputs
Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and 8
Shared programmable multiplier x2, x3, and x4
Support pin mode options to configure the device without SPI
LOGICLK output with corresponding SYSREF output
On separate divide bank
1, 2, 4 pre-divider
1 (bypass), 2, …, 1023 post divider
8 programmable output power levels
Synchronized SYSREF clock outputs
508 delay step adjustments of less than 2.5ps each at 12.8GHz
Generator and repeater modes
Windowing feature for SYSREFREQ pins to optimize timing
SYNC feature to all divides and multiple devices
2.5V operating voltage
–55ºC to 125ºC operating temperature
High Reliability
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Extended Product Life Cycle
Product Traceability