SNAS883 June 2024 LMX1860-SEP
PRODUCTION DATA
The device can configure in high frequency clock buffer mode, divider mode or multiplier mode. Each mode requires the below register configurations to function.
REGISTER ADDRESS | BIT | FIELD | FUNCTION | BUFFER | DIVIDER | MULTIPLIER |
---|---|---|---|---|---|---|
R25 | 2:0 | CLK_MUX | Select the mode | 1 | 2 | 3 |
R25 | 5:3 | CLK_DIV / CLK_MULT | Select the division or multiplication value | x | CLK_DIV 0x1 = ÷2 0x2 = ÷3 0x3 = ÷4 0x4 = ÷5 0x5 = ÷6 0x6 = ÷7 0x7 = ÷8 | CLK_MULT 0x2 = ×2 0x3 = ×3 0x4 = ×4 |
R2 | 5 | SMCLK_EN | Enables the state machine clock generator | x | x | 1 |
R2 | 9:6 | SMCLK_DIV_PRE | Sets pre-divider for state machine clock | x | x | Pre-clock divider for state machine clock 0x2 = ÷2 0x4 = ÷4 0x8 = ÷8 |
R3 | 2:0 | SMCLK_DIV | Sets state machine clock divider | x | x | Additional SMCLK divider to keep output frequency must be ≤ 30MHz. 0x0 = ÷1 0x1 = ÷2 0x2 = ÷4 0x3 = ÷8 0x4 = ÷16 0x5 = ÷32 0x6 = ÷64 0x7 = ÷128 |
R0 | All | Calibrate Multiplier | Calibrate the PLL based multiplier | x | x | Write R0 for calibrate multiplier |