SNAS883 June 2024 LMX1860-SEP
PRODUCTION DATA
There are dividers that allow the main and LOGICLK outputs to be a divided value of the input clock. The main clock outputs also have a multiplier. In addition to this, dividers are used for SYSREF generation in generator mode as well as generation of the delay block.
CATEGORY | RANGE | COMMENTS | ||
---|---|---|---|---|
Main Clocks | Buffer | |||
Divider(1) | 2, 3, 4, … 8 | Odd divides (except 1) do not have 50% duty cycle | ||
Multiplier | 2, 3, 4 | |||
LOGICLK | Divide | PreDivide | 1, 2, 4 | TotalDivide = PreDivide
× Divide Odd divides (except 1) do not have 50% duty cycle |
Divide | 1, 2, 3, … 1023 | |||
SYSREF | Divide for frequency generation | PreDivide | 1,2, 4 | Pre-divides clock for
SYSREF generation.TotalDivide = PreDivide×Divide Odd divides do not have 50% duty cycle |
Divide | 2, 3, 4,… 4095 | |||
Divide for delay generation | Divide | 2, 4, 8, 16 | This divide is for phase interpolator and set according to the input frequency. |