SNAS883 June   2024 LMX1860-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ Pins and SYSREFREQ_FORCE Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Generation (Retime)
            3. 6.3.6.3.2.3 Other Guidance For SYSREF Windowing
            4. 6.3.6.3.2.4 For Glitch-Free Output
            5. 6.3.6.3.2.5 If Using SYNC Feature
          3. 6.3.6.3.3 SYNC Feature
      7. 6.3.7 Pin Mode Control
        1. 6.3.7.1 Chip Enable (CE)
        2. 6.3.7.2 Output Channel Control
        3. 6.3.7.3 Logic Output Control
        4. 6.3.7.4 SYSREF Output Control
        5. 6.3.7.5 Device Mode Selection
        6. 6.3.7.6 Divider or Multiplier Value Selection
        7. 6.3.7.7 Calibration Control Pin
        8. 6.3.7.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plot
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power-Up Timing
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.6.2 SYSREF Frequency and Delay Generation

For the frequency of the SYSREF output in generator mode, the SYSREF_DIV_PRE divider is necessary to verify that the input of the SYSREF_DIV divider is not more than 3.2GHz.

Table 6-11 SYSREF_DIV_PRE Setup
fCLKIN SYSREF_DIV_PRE TOTAL SYSREF DIVIDE RANGE
3.2GHz or Less ÷1, 2, or 4 ÷2, 3, 4, ...16380
3.2GHz < fCLKIN ≤ 6.4GHz ÷2 or 4 ÷4, 6, 8, … 16380
fCLKIN > 6.4GHz ÷4 ÷8, 12, 16, … 16380

For the delay, the input clock frequency is divided by SYSREF_DLY_DIV to generate fINTERPOLATOR. This has a restricted range as shown in Table 6-12. Note also that when SYSREF_DLY_BYP = 0 or 2 (delaygen engaged for generator mode), and SYSREF_MODE = 0 or 1 (a generator mode) the SYSREF output frequency must be a multiple of the phase interpolator frequency.

fINTERPOLATOR % fSYSREF = 0.

Table 6-12 SYSREF Delay Setup
fCLKIN SYSREF_DLY_DIV SYSREFx_DLY_SCALE fINTERPOLATOR
6.4GHz < fCLKIN ≤ 12.8GHz 16 0 0.4GHz to 0.8GHz
3.2GHz < fCLKIN ≤ 6.4GHz 8 0 0.4GHz to 0.8GHz
1.6GHz < fCLKIN ≤ 3.2GHz 4 0 0.4GHz to 0.8GHz
0.8GHz < fCLKIN ≤ 1.6GHz 2 0 0.4GHz to 0.8GHz
0.4GHz < fCLKIN ≤ 0.8GHz 2 1 0.2GHz to 0.4GHz
0.3GHz < fCLKIN ≤ 0.4GHz 2 2 0.15GHz to 0.2GHz

The maximum delay is equal to the phase interpolator period and there are 4 × 127 = 508 different delay steps. Use Equation 2 to calculate the size of each step.

Equation 2. DelayStepSize = 1 / ( fINTERPOLATOR × 508) = SYSREF_DLY_DIV / ( fCLKIN × 508)

Use Equation 3 to calculate the total delay.

Equation 3. TotalDelay = DelayStepSize × StepNumber

Table 6-13 shows the number of steps for each delay.

Table 6-13 Calculation of StepNumber
SYSREFx_DLY_PHASE STEPNUMBER
3 127 - SYSREFx_DLY_I
2 254 - SYSREFx_DLY_Q
0 381 - SYSREFx_DLY_I
1 508 - SYSREFx_DLY_Q

The SYSREF_DLY_BYP field selects the delay path in SYSREF generation output and or the repeater mode bypass signal. When SYSREF_MODE is set to continuous or pulser mode, TI recommends to set SYSREF_DLY_BYP to generator mode. If SYSREF_MODE is set to repeater mode, TI recommends to set SYSREF_DLY_BYP to bypass mode.