SNAS883 June 2024 LMX1860-SEP
PRODUCTION DATA
The LOGICLK_DIV_PRE divider and LOGICLK_DIV dividers are used for the LOGICLK output. The LOGICLK_DIV_PRE divider is necessary to divide the frequency down to verify that the input to the LOGICLK_DIV divider is 3.2GHz or less. When LOGICLK_DIV is not even and not bypassed, the duty cycle is not 50%. Both the LOGICLK dividers are synchronized by the SYNC feature, which allows synchronization across multiple devices. The dividers LOGICLK_DIV_PRE and LOGICLK_DIV has the default divide value of 4 and 32 respectively.
fCLKIN (MHz) | LOGICLK_DIV_PRE | LOGICLK_DIV | TOTAL DIVIDE RANGE |
---|---|---|---|
fCLKIN ≤ 3.2GHz | ÷1, 2, 4 | ÷1, 2, 3,…1023 | [1, 2, ...1023] [2, 4, ... 2046] [4, 8, 4092] |
3.2GHz < fCLKIN≤ 6.4GHz | ÷2, 4 | ÷1, 2, 3, …1023 | [4, ... 2046] [4, 8, 4092] |
fCLKIN > 6.4GHz | ÷4 | 1, 2, 3, …1023 | [8, 4092] |