SNAS851 December 2023 LMX1906-SP
PRODUCTION DATA
Table 7-4 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 7-4 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | R0 | Section 7.5.1.1 | |
2h | R2 | Section 7.5.1.2 | |
3h | R3 | Section 7.5.1.3 | |
4h | R4 | Section 7.5.1.4 | |
5h | R5 | Section 7.5.1.5 | |
6h | R6 | Section 7.5.1.6 | |
7h | R7 | Section 7.5.1.7 | |
8h | R8 | Section 7.5.1.8 | |
9h | R9 | Section 7.5.1.9 | |
Bh | R11 | Section 7.5.1.10 | |
Ch | R12 | Section 7.5.1.11 | |
Dh | R13 | Section 7.5.1.12 | |
Eh | R14 | Section 7.5.1.13 | |
Fh | R15 | Section 7.5.1.14 | |
10h | R16 | Section 7.5.1.15 | |
11h | R17 | Section 7.5.1.16 | |
12h | R18 | Section 7.5.1.17 | |
13h | R19 | Section 7.5.1.18 | |
14h | R20 | Section 7.5.1.19 | |
15h | R21 | Section 7.5.1.20 | |
16h | R22 | Section 7.5.1.21 | |
17h | R23 | Section 7.5.1.22 | |
18h | R24 | Section 7.5.1.23 | |
19h | R25 | Section 7.5.1.24 | |
1Ch | R28 | Section 7.5.1.25 | |
1Dh | R29 | Section 7.5.1.26 | |
21h | R33 | Section 7.5.1.27 | |
22h | R34 | Section 7.5.1.28 | |
41h | R65 | Section 7.5.1.29 | |
43h | R67 | Section 7.5.1.30 | |
48h | R72 | Section 7.5.1.31 | |
49h | R73 | Section 7.5.1.32 | |
4Bh | R75 | Section 7.5.1.33 | |
4Ch | R76 | Section 7.5.1.34 | |
56h | R86 | Section 7.5.1.35 | |
5Ah | R90 | Section 7.5.1.36 |
Complex bit access types are encoded to fit into small table cells. Table 7-5 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
R0 is shown in Table 7-6.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
2 | POWERDOWN | R/W | 0h | Sets the device in a low-power state. The states of other registers are maintained. |
1 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
0 | RESET | R/W | 0h | Soft Reset. Resets the entire logic and registers (equivalent to power-on reset). Self-clearing on next register write. |
R2 is shown in Table 7-7.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
10 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
9-6 | SMCLK_DIV_PRE | R/W | 8h | Pre-divider for State Machine clock (one hot divider).The state machine clock is divided from the input clock. The output of the pre-divider should be ≤1600MHz. Values other than those listed are reserved.
2h = /2 4h = /4 8h = /8 |
5 | SMCLK_EN | R/W | 1h | Enables the state machine clock generator. Only required to calibrate the multiplier, and for multiplier lock detect (including on MUXOUT pin). If the multiplier is not used, or if the multiplier lock detect feature is not used, the state machine clock generator can be disabled to minimize crosstalk. |
4-0 | UNDISCLOSED | R/W | 3h | Program this field to 0x3. |
R3 is shown in Table 7-8.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | CH3_EN | R/W | 1h | Enables CH3 (CLKOUT3, SYSOUT3). Setting this bit to 0 will completely disable CH3, overriding the state of other power-down/enable bits. |
14 | CH2_EN | R/W | 1h | Enables CH2 (CLKOUT2, SYSOUT2). Setting this bit to 0 will completely disable CH2, overriding the state of other power-down/enable bits. |
13 | CH1_EN | R/W | 1h | Enables CH1 (CLKOUT1, SYSOUT1). Setting this bit to 0 will completely disable CH1, overriding the state of other power-down/enable bits. |
12 | CH0_EN | R/W | 1h | Enables CH0 (CLKOUT0, SYSOUT0). Setting this bit to 0 will completely disable CH0, overriding the state of other power-down/enable bits. |
11 | LOGICLK_MUTE_CAL | R/W | 1h | Mutes LOGIC outputs (LOGICLK/LOGISYS) during multiplier calibration. |
10 | CH3_MUTE_CAL | R/W | 1h | Mutes CH3 (CLKOUT3/SYSOUT3) during multiplier calibration. |
9 | CH2_MUTE_CAL | R/W | 1h | Mutes CH2 (CLKOUT2/SYSOUT2) during multiplier calibration. |
8 | CH1_MUTE_CAL | R/W | 1h | Mutes CH1 (CLKOUT1/SYSOUT1) during multiplier calibration. |
7 | CH0_MUTE_CAL | R/W | 1h | Mutes CH0 (CLKOUT0/SYSOUT0) during multiplier calibration. |
6-3 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
2-0 | SMCLK_DIV | R/W | 6h | Sets state machine clock divider. Further divides the output of the state machine clock pre-divider. Input frequency from SMCLK_DIV_PRE must be ≤ 1600 MHz. Output frequency must be ≤ 30 MHz. Divide value is 2SMCLK_DIV.
0h = /1 1h = /2 2h = /4 3h = /8 4h = /16 5h = /32 6h = /64 7h = /128 |
R4 is shown in Table 7-9.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
13-11 | CLKOUT1_PWR | R/W | 6h | Sets the output power of CLKOUT1. Larger values correspond to higher output power. |
10-8 | CLKOUT0_PWR | R/W | 6h | Sets the output power of CLKOUT0. Larger values correspond to higher output power. |
7 | SYSREFOUT3_EN | R/W | 1h | Enables SYSREFOUT3 output buffer. |
6 | SYSREFOUT2_EN | R/W | 1h | Enables SYSREFOUT2 output buffer. |
5 | SYSREFOUT1_EN | R/W | 1h | Enables SYSREFOUT1 output buffer. |
4 | SYSREFOUT0_EN | R/W | 1h | Enables SYSREFOUT0 output buffer. |
3 | CLKOUT3_EN | R/W | 1h | Enables CLKOUT3 output buffer. |
2 | CLKOUT2_EN | R/W | 1h | Enables CLKOUT2 output buffer. |
1 | CLKOUT1_EN | R/W | 1h | Enables CLKOUT1 output buffer. |
0 | CLKOUT0_EN | R/W | 1h | Enables CLKOUT0 output buffer. |
R5 is shown in Table 7-10.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
14-12 | SYSREFOUT2_PWR | R/W | 4h | Sets the output power of SYSREFOUT2. Larger values correspond to higher output power. SYSREFOUT2_VCM must be set properly to bring the output common mode voltage within permissible limits. |
11-9 | SYSREFOUT1_PWR | R/W | 4h | Sets the output power of SYSREFOUT1. Larger values correspond to higher output power. SYSREFOUT1_VCM must be set properly to bring the output common mode voltage within permissible limits. |
8-6 | SYSREFOUT0_PWR | R/W | 4h | Sets the output power of SYSREFOUT0. Larger values correspond to higher output power. SYSREFOUT0_VCM must be set properly to bring the output common mode voltage within permissible limits. |
5-3 | CLKOUT3_PWR | R/W | 6h | Sets the output power of CLKOUT3. Larger values correspond to higher output power. |
2-0 | CLKOUT2_PWR | R/W | 6h | Sets the output power of CLKOUT2. Larger values correspond to higher output power. |
R6 is shown in Table 7-11.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LOGICLKOUT_EN | R/W | 1h | Enables the logic clock output buffer. |
14-12 | SYSREFOUT3_VCM | R/W | 3h | Sets the output common mode of SYSREFOUT3. SYSREFOUT3_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits. |
11-9 | SYSREFOUT2_VCM | R/W | 3h | Sets the output common mode of SYSREFOUT2. SYSREFOUT2_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits. |
8-6 | SYSREFOUT1_VCM | R/W | 3h | Sets the output common mode of SYSREFOUT1. SYSREFOUT1_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits. |
5-3 | SYSREFOUT0_VCM | R/W | 3h | Sets the output common mode of SYSREFOUT0. SYSREFOUT0_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits. |
2-0 | SYSREFOUT3_PWR | R/W | 4h | Sets the output power of SYSREFOUT3. Larger values correspond to higher output power. SYSREFOUT3_VCM must be set properly to bring the output common mode voltage within permissible limits. |
R7 is shown in Table 7-12.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
14-13 | LOGISYSREFOUT_VCM | R/W | 0h | In LVDS mode, sets the output common mode of the logic SYSREF output. Other output formats ignore this field.
0h = 1.2V 1h = 1.1V 2h = 1.0V 3h = 0.9V |
12-11 | LOGICLKOUT_VCM | R/W | 0h | In LVDS mode, sets the output common mode of the logic clock output. Other output formats ignore this field.
0h = 1.2V 1h = 1.1V 2h = 1.0V 3h = 0.9V |
10-9 | LOGISYSREF_DIV_PWR_PRE | R/W | 0h | Sets the output power of the logic SYSREF pre-driver. Larger values correspond to higher output power. |
8-7 | LOGICLK_DIV_PWR_PRE | R/W | 0h | Sets the output power of the logic clock pre-driver. Larger values correspond to higher output power. |
6-4 | LOGISYSREFOUT_PWR | R/W | 0h | Sets the output power of LOGISYSREFOUT for CML format only (other output formats ignore this field). Larger values correspond to higher output power. |
3-1 | LOGICLKOUT_PWR | R/W | 0h | Sets the output power of LOGICLKOUT for CML format only (other output formats ignore this field). Larger values correspond to higher output power. |
0 | LOGISYSREFOUT_EN | R/W | 1h | Enables the logic SYSREF output buffer. |
R8 is shown in Table 7-13.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
8-6 | LOGICLK_DIV_PRE | R/W | 4h | Sets pre-divider value for logic clock divider. Output of the pre-divider must be less than or equal to 3.2 GHz. When LOGICLK_DIV_PRE=1, it is also required register R79 is programmed to a value of 0x0005 and R90 to 0x0060 (LOGICLK_DIV_BYP2=1, LOGICLK_DIV_BYP3=1). Values for LOGICLK_DIV_PRE other than those listed below are reserved.
1h = /1 2h = /2 4h = /4 |
5 | LOGIC_EN | R/W | 1h | Enables LOGICLK subsystem (LOGICLKOUT, LOGISYSREFOUT). Setting this bit to 0x0 completely disables all LOGICLKOUT and LOGISYSREFOUT circuitry, overriding the state of other power-down/enable bits. |
4 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
3-2 | LOGISYSREFOUT_FMT | R/W | 0h | Selects the output driver format of the LOGISYSREFOUT output.
0h = LVDS 1h = Reserved 2h = CML 3h = Reserved |
1-0 | LOGICLKOUT_FMT | R/W | 0h | Selects the output driver format of the LOGICLKOUT output.
0h = LVDS 1h = Reserved 2h = CML 3h = Reserved |
R9 is shown in Table 7-14.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | SYSREFREQ_VCM | R/W | 0h | Sets the internal DC Bias for the SYSREFREQ pins. Bias must be enabled for AC-coupled inputs; but can be enabled and overdriven, or disabled, for DC-coupled inputs. SYSREFREQ DC pin voltage must be in the range of 0.7 V to VCC, including minimum and maximum signal swing.
0h = 1.3V 1h = 1.1V 2h = 1.5V 3h = Disabled |
13 | SYNC_EN | R/W | 0h | Enables synchronization path for the dividers and allows the clock position capture circuitry to be enabled. Used for multi-device synchronization. Redundant if SYSREF_EN = 0x1. |
12 | LOGICLK_DIV_PD | R/W | 0h | Disables the LOGICLK divider. LOGICLK pre-divider remains enabled. Used to reduce current consumption when bypassing the LOGICLK divider. |
11 | LOGICLK_DIV_BYP | R/W | 0h | Bypasses the LOGICLK_DIV divider in order to derive the LOGICLK output directly
from the LOGICLK_DIV_PRE divider. Should only be
used when LOGICLK_DIV_PRE=1 as one of the steps to
achieve a total divide of 1 for the LOGICLK. In
order to achieve a divide by 1, the following steps
are required. 1. Set LOGICLK_DIV_PRE=1 2. Ensure that register R79 is programmed to a value of 0x0005 3. Program R90 to 0x0060 (LOGICLK_DIV23=1, LOGICLK_DIV_DCC=1) 4. Set LOGICLK_DIV_BYP=1 When not wanting a total divide of 1 for the LOGICLK, this bit should be set to 0. 0h = Engage LOGICLK divider 1h = Bypass LOGICLK divider |
10 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
9-0 | LOGICLK_DIV | R/W | 20h | Sets LOGICLK divider value. Maximum input frequency from LOGICLK_DIV_PRE must be ≤ 3200 MHz. The maximum LOGICLKOUT frequency must be ≤ 800 MHz to avoid amplitude degradation.
0h = Reserved 1h = Reserved 2h = /2 3h = /3 3FFh = /1023 |
R11 is shown in Table 7-15.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | rb_CLKPOS | R | 0h | Stores a snapshot of the CLKIN signal rising edge positions relative to a SYSREFREQ rising edge, with the snapshot starting from the LSB and ending at the MSB. Each bit represents a sample of the CLKIN signal, separated by a delay determined by the SYSREFREQ_DLY_STEP field. The first and last bits of rb_CLKPOS are always set, indicating uncertainty at the capture window boundary conditions. CLKIN rising edges are represented by every sequence of two set bits from LSB to MSB, including bits at the boundary conditions. The position of the CLKIN rising edges in the snapshot, along with the CLKIN signal period and the delay step size, can be used to compute the value of SYSREFREQ_DLY which maximizes setup and hold times for SYNC signals on the SYSREFREQ pins. |
R12 is shown in Table 7-16.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | rb_CLKPOS[31:16] | R | 0h | MSB of rb_CLKPOS field. |
R13 is shown in Table 7-17.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-2 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
1-0 | SYSREFREQ_DLY_STEP | R/W | 3h | Sets the step size of the delay element used in the SYSREFREQ path, both for SYSREFREQ input delay and for clock position captures. The recommended frequency range for each step size creates the maximum number of usable steps for a given CLKIN frequency. The ranges include some overlap to account for process and temperature variations. If the CLKIN frequency is covered by an overlapping span, larger delay step sizes improve the likelihood of detecting a CLKIN rising edge during a clock position capture. However, since larger values include more delay steps, larger step sizes have greater total delay variation across PVT relative to smaller step sizes.
0h = 28 ps (1.4GHz to 2.7GHz) 1h = 15 ps ( 2.4GHz to 4.7GHz) 2h = 11 ps (3.1GHz to 5.7GHz) 3h = 8 ps (4.5GHz to 12.8GHz) |
R14 is shown in Table 7-18.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
8 | SYNC_MUTE_PD | R/W | 0h | Removes the mute condition on the SYSREFOUT and LOGISYSREFOUT pins during SYNC mode (SYSREFREQ_MODE = 0x0). Since the SYNC operation also resets the SYSREF dividers, the mute condition is usually desirable, and this bit can be left at the default value. |
7-3 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
2 | CLKPOS_CAPTURE_EN | R/W | 0h | Enables the windowing circuit which captures the clock position in the rb_CLKPOS registers with respect to a SYSREF edge. The windowing circuit must be cleared by toggling SYSREFREQ_CLR high then low before a clock position capture. The first rising edge on the SYSREFREQ pins after clearing the windowing circuit triggers the capture. The capture circuitry greatly increases supply current, and does not need to be enabled to delay the SYSREFREQ signal in SYNC or SYSREF modes. Once the desired value of SYSREFREQ_DLY is determined, set this bit to 0x0 to minimize current consumption. If SYNC_EN = 0 and SYSREF_EN = 0, the value of this bit is ignored, and the windowing circuit is disabled. |
1 | SYSREFREQ_MODE | R/W | 1h | Selects the function of the SYSREFREQ pins
0h = SYNC pin 1h = SYSREFREQ pin |
0 | SYSREFREQ_LATCH | R/W | 0h | Latches the internal SYSREFREQ state to logic high on the first rising edge of the SYSREFREQ pins. This latch can be cleared by setting SYSREFREQ_CLR=1. |
R15 is shown in Table 7-19.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
11-10 | SYSREF_DIV_PRE | R/W | 2h | Sets the SYSREF pre-divider. Maximum output frequency must be ≤ 3.2GHz.
0h = /1 1h = /2 2h = /4 3h = Reserved |
9 | UNDISCLOSED | R/W | 1h | Program this field to 0x1. |
8 | SYSREF_EN | R/W | 1h | Enables SYSREF subsystem (and SYNC subsystem when SYSREFREQ_MODE = 0x0). Setting this bit to 0x0 completely disables all SYNC, SYSREF, and clock position capture circuitry, overriding the state of other power-down/enable bits except SYNC_EN. If SYNC_EN = 0x1, the SYNC path and clock position capture circuitry are still enabled, regardless of the state of SYSREF_EN. |
7 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
6-1 | SYSREFREQ_DLY | R/W | 0h | Sets the delay line step for the external SYSREFREQ signal. Each delay line step delays the SYSREFREQ signal by an amount equal to SYSREFREQ_DELAY_STEP x SYSREFREQ_DLY_STEP. In SYNC mode, the value for this field can be determined based on the rb_CLKPOS value to satisfy the internal setup and hold time of the SYNC signal with respect to the CLKIN signal. In SYSREF Repeater Mode, the value for this field can be used as a coarse global delay. Values greater than 0x3F are invalid. Since larger values include more delay steps, larger values have greater total step size variation across PVT relative to smaller values. Refer to the data sheet or the device TICS Pro profile for detailed description of the delay step computation procedure. |
0 | SYSREFREQ_CLR | R/W | 1h | Clears SYSREFREQ_LATCH and resets synchronization path timing for SYSREFREQ signal. Holding this bit high keeps internal SYSREFREQ signal low in all modes except SYSREF repeater mode, overriding the state of SYSREFREQ_FORCE. This bit must be set and cleared once before the SYNC or clock position capture operations are performed. |
R16 is shown in Table 7-20.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | SYSREF_PULSE_CNT | R/W | 1h | Programs the number of pulses generated in pulser mode. The pulser is a counter gating the SYSREF divider; consequently, the pulse duration and frequency are equal to the duty cycle and frequency of the SYSREF divider output, respectively.
0h = Reserved 1h = 1 pulse 2h = 2 pulses Fh = 15 pulses |
11-0 | SYSREF_DIV | R/W | 5h | Sets the SYSREF divider. Maximum input frequency from SYSREF_DIV_PRE must be ≤ 3200 MHz. Maximum output frequency must be ≤ 100 MHz. Odd divides (with duty cycle < 50%) are only allowed when the delay generators are bypassed.
0h = Reserved 1h = Reserved 2h = /2 3h = /3 FFFh = /4095 |
R17 is shown in Table 7-21.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
10-4 | SYSREF0_DLY_I | R/W | 7Fh | Sets the delay step for the SYSREFOUT0 delay generator. Must satisfy SYSREFOUT0_DLY_I + SYSREFOUT0_DLY_Q = 127 |
3-2 | SYSREF0_DLY_PHASE | R/W | 0h | Sets the quadrature phase of the interpolator clock used for the SYSREFOUT0 delay generator retimer.
0h = ICLK' 1h = QCLK' 2h = ICLK 3h = QCLK |
1-0 | SYSREF_MODE | R/W | 0h | Controls how the SYSREF signal is generated and is also impacted by the
SYSREF_DLY_BYP field. Continuous mode generates a
continuous SYSREF clock that is derived from the
SYSREF divdier and delay. In pulser mode, a pulse at
the SYSREFREQ pin causes a specific number
(determined by SYSREF_PULSE_CNT) of pulses to be
generated for the SYSREF outputs. In Repeater mode,
a pulse at the SYSREFREQ pins will generate a single
pulse at the SYSREF outputs and only the propagation
delay through the device is added. 0h = Continuous 1h = Pulser 2h = Repeater 3h = Reserved |
R18 is shown in Table 7-22.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | SYSREF1_DLY_I | R/W | 7Fh | Sets the delay step for the SYSREFOUT0 delay generator. Must satisfy SYSREFOUT0_DLY_I + SYSREFOUT0_DLY_Q = 127 |
8-7 | SYSREF1_DLY_PHASE | R/W | 0h | Sets the quadrature phase of the interpolator clock used for the SYSREFOUT1 delay generator retimer.
0h = ICLK' 1h = QCLK' 2h = QCLK 3h = ICLK |
6-0 | SYSREF0_DLY_Q | R/W | 0h | Determines the strength of QCLK for delay generation. Must satisfy SYSREF0_DLY_I + SYSREF0_DLY_Q = 127 |
R19 is shown in Table 7-23.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | SYSREF2_DLY_I | R/W | 7Fh | Determines the strength of ICLK for delay generation. Must satisfy SYSREF2_DLY_I + SYSREF2_DLY_Q = 127 |
8-7 | SYSREF2_DLY_PHASE | R/W | 0h | Sets the quadrature phase of the interpolator clock used for the SYSREFOUT2 delay generator retimer.
0h = ICLK' 1h = QCLK' 2h = QCLK 3h = ICLK |
6-0 | SYSREF1_DLY_Q | R/W | 0h | Determines the strength of QCLK for delay generation. Must satisfy SYSREF1_DLY_I + SYSREF1_DLY_Q = 127 |
R20 is shown in Table 7-24.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | SYSREF3_DLY_I | R/W | 7Fh | Sets the delay step for the SYSREFOUT1 delay generator. Must satisfy SYSREFOUT1_DLY_I + SYSREFOUT1_DLY_Q = 127 |
8-7 | SYSREF3_DLY_PHASE | R/W | 0h | Sets the quadrature phase of the interpolator clock used for the SYSREFOUT3 delay generator retimer.
0h = ICLK' 1h = QCLK' 2h = QCLK 3h = ICLK |
6-0 | SYSREF2_DLY_Q | R/W | 0h | Determines the strength of QCLK for delay generation. Must satisfy SYSREF3_DLY_I + SYSREF3_DLY_Q = 127 |
R21 is shown in Table 7-25.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | LOGISYSREF_DLY_I | R/W | 7Fh | Determines the strength of logic ICLK for delay generation. Must satisfy LOGISYSREF_DLY_I+LOGISYSREF_DLY_Q = 127 |
8-7 | LOGISYSREF_DLY_PHASE | R/W | 0h | Sets the quadrature phase of the interpolator clock used for the LOGISYSREFOUT delay generator retimer.
0h = ICLK' 1h = QCLK' 2h = QCLK 3h = ICLK |
6-0 | SYSREF3_DLY_Q | R/W | 0h | Determines the strength of QCLK for delay generation. Must satisfy SYSREFx_DLY_I + SYSREFx_DLY_Q = 127 |
R22 is shown in Table 7-26.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | SYSREF1_DLY_SCALE | R/W | 0h | Sets the frequency range of the SYSREFOUT1 delay generator. Set according to phase interpolator frequency.
0h = 400MHz to 800MHz 1h = 200MHz to 400MHz 2h = 150MHz to 200MHz 3h = Reserved |
13-12 | SYSREF0_DLY_SCALE | R/W | 0h | Sets the frequency range of the SYSREFOUT0 delay generator. Set according to phase interpolator frequency.
0h = 400MHz to 800MHz 1h = 200MHz to 400MHz 2h = 150MHz to 200MHz 3h = Reserved |
11-9 | SYSREF_DLY_DIV | R/W | 4h | Sets the delay generator clock division, determining the phase interpolator frequency and the delay generator resolution. Values other than those listed below are reserved. 0h = /1 (Up to 1.6GHz) 1h = /2 (1.6GHz to 3.2GHz) 2h = /4 (3.2GHz to 6.4GHz) 4h = /8 (6.4GHz to 12.8GHz) |
8-7 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
6-0 | LOGISYSREF_DLY_Q | R/W | 0h | Sets the delay step for the LOGISYSREFOUT delay generator. Must satisfy LOGISYSREFOUT_DLY_I + LOGISYSREFOUT_DLY_Q = 127. |
R23 is shown in Table 7-27.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | TS_EN | R/W | 0h | Enables the on-die temperature sensor. Temperature sensor counter (TS_CNT_EN) must also be enabled for readback. |
14 | UNDISCLOSED | R/W | 1h | Program this field to 0x1. |
13 | MUXOUT_EN | R/W | 0h | Enables or tri-states the MUXOUT pin driver.
0h = Tri-States 1h = Push-Pull |
12-7 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
6 | MUXOUT_SEL | R/W | 0h | Selects MUXOUT pin function.
0h = Lock Detect 1h = Readback |
5-4 | LOGISYSREF_DLY_SCALE | R/W | 0h | Sets the frequency range of the LOGISYSREFOUT delay generator. Set according to phase interpolator frequency.
0h = 400MHz to 800MHz 1h = 200MHz to 400MHz 2h = 150MHz to 200MHz 3h = Reserved |
3-2 | SYSREF3_DLY_SCALE | R/W | 0h | Sets the frequency range of the SYSREFOUT3 delay generator. Set according to phase interpolator frequency.
0h = 400MHz to 800MHz 1h = 200MHz to 400MHz 2h = 150MHz to 200MHz 3h = Reserved |
1-0 | SYSREF2_DLY_SCALE | R/W | 0h | Sets the frequency range of the SYSREFOUT2 delay generator. Set according to phase interpolator frequency.
0h = 400MHz to 800MHz 1h = 200MHz to 400MHz 2h = 150MHz to 200MHz 3h = Reserved |
R24 is shown in Table 7-28.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
13-12 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
11-1 | rb_TS | R | 0h | Readback value of on-die temperature sensor. |
0 | TS_CNT_EN | R/W | 0h | Enables temperature sensor counter. Temperature sensor (EN_TS) must be enabled for accurate data. |
R25 is shown in Table 7-29.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-7 | UNDISCLOSED | R/W | 4h | Program this field to 0x4. |
6 | CLK_DIV_RST | R/W | 0h | Resets the main clock divider. If the clock divider value is changed during operation, set this bit high then low after setting the new divider value. Synchronizing the device with the SYSREFREQ pins in SYSREFREQ_MODE = 0x0 and SYNC_EN = 0x1 also resets the main clock divider. This bit has no effect when outside of Divider Mode. |
5-3 | CLK_DIV | R/W | 2h | CLK_DIV and CLK_MULT are aliases for the same field. When CLK_MUX=1 (Buffer Mode), this field is ignored. When CLK_MUX = 2 (Divider Mode), the clock divider is CLK_DIV + 1. Valid range for CLK_DIV is 1 to 7. Setting this to 0 disables the main clock divider and reverts to buffer mode. When CLK_MUX = 3 (Multiplier Mode), CLK_MULT the multiplier value is CLK_MULT. Valid range is 1 to 4. Setting outside this range disables multiplier mode and reverts to buffer mode. Valid range is 0x1 to 0x4. |
2-0 | CLK_MUX | R/W | 1h | Selects the function for the main clock outputs
0h = Reserved 1h = Buffer 2h = Dividers 3h = Multiplier |
R28 is shown in Table 7-30.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
12 | VCO_CORE_FORCE | R/W | 0h | Forces the multiplier PLL's VCO to the value selected by VCO_CORE. Not required for Multiplier Mode programming, but can optionally be used to reduce calibration time. |
11-9 | VCO_CORE | R/W | 5h | When VCO_CORE_FORCE=0, specifies start VCO for multiplier calibration. When VCO_CORE_FORCE=1, this VCO core is forced. Programming of this field is not required for Multiplier Mode programming, but can be used to debugging purposes or to reduce calibration time. |
8-0 | UNDISCLOSED | R/W | 8h | Program this field to 0x8. |
R29 is shown in Table 7-31.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
12-8 | UNDISCLOSED | R/W | 5h | Program this field to 0x5. |
7-0 | VCO_CAPCTRL | R/W | FFh | Sets the starting value for the VCO tuning capacitance during multiplier calibration. Not required for Multiplier Mode programming, but can be used to reduce calibration time. |
R33 is shown in Table 7-32.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | UNDISCLOSED | R/W | 7777h | Program this field to 0x6666. Note that this is different than the reset value. |
R34 is shown in Table 7-33.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
13-0 | UNDISCLOSED | R/W | 7h | Program this field to 0x5. Note that this is different than the reset value. |
R65 is shown in Table 7-34.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | UNDISCLOSED | R/W | 32h | Program this field to 0x32. |
8-4 | rb_VCO_CORE | R | 1Fh | Readback for the multiplier VCO Core. There are only valid values and the VCO is determined by the bit that is low.
Fh = VCO1 17h = VCO2 1Bh = VCO3 1Dh = VCO4 1Eh = VCO5 |
3-0 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
R67 is shown in Table 7-35.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | UNDISCLOSED | R/W | 50C8h | Program this field to 0x51CB. Note that this is different than the reset value. |
R72 is shown in Table 7-36.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
14-3 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
2 | SYSREFREQ_FORCE | R/W | 0h | Setting this bit emulates the behavior of a logic HIGH at SYSREFREQ pins and causes external signals on SYSREFREQ pins to be ignored. |
1-0 | SYSREF_DLY_BYP | R/W | 0h | Option to bypass delay generator retiming. Under normal circumstances
(SYSREF_DLY_BYP = 0) the delay generator is engaged
for continuous or pulser modes (Generator Modes),
and bypassed in Repeater Mode. Generally this
typically utilize a different delay mechanism. In
certain cases, bypassing the delay generator
retiming in Generator Mode by setting SYSREF_DLY_BYP
= 1 can substantially reduce the device current
consumption if the SYSREF delay can be compensated
at the JESD receiver. In other cases, retiming the
SYSREFREQ signal to the delay generators by setting
SYSREF_DLY_BYP = 2 can improve the accuracy of the
SYSREF output phase with respect to the CLKIN phase,
or can vary the delay of individual outputs independently, as long as coherent phase relationship exists between the interpolator divider phase and the SYSREFREQ phase. 0h = Engage in Generator Mode, Bypass in Repeater Mode 1h = Bypass in All Modes 2h = Engage in All Modes 3h = Reserved |
R73 is shown in Table 7-37.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
12-0 | UNDISCLOSED | R/W | 0h | Program this field to 0x1000. Note that this is different than the reset value. |
R75 is shown in Table 7-38.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | rb_CLK2_EN | R | 0h | Readback Pin Status |
14 | rb_CLK1_EN | R | 0h | Readback Pin Status |
13 | rb_CLK0_EN | R | 0h | Readback Pin Status |
12 | rb_MUXSEL1 | R | 0h | Readback Pin Status |
11 | rb_MUXSEL0 | R | 0h | Readback Pin Status |
10 | rb_LOGIC_EN | R | 0h | Readback Pin Status |
9-8 | rb_LD | R | 0h | Readback for Multiplier PLL lock detect.
0h = Unlocked (VTUNE low) 1h = Reserved 2h = Locked 3h = Unlocked (VTUNE high) |
7 | rb_DIVSEL2 | R | 0h | Readback Pin Status |
6 | rb_DIVSEL1 | R | 0h | Readback Pin Status |
5 | rb_DIVSEL0 | R | 0h | Readback Pin Status |
4 | rb_CE | R | 0h | Readback Pin Status |
3-0 | UNDISCLOSED | R/W | 6h | Program this field to 0x3. Note that this is different than the reset value. |
R76 is shown in Table 7-39.
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Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
3 | rb_PWRSEL2 | R | 0h | Readback Pin Status |
2 | rb_PWRSEL1 | R | 0h | Readback Pin Status |
1 | rb_PWRSEL0 | R | 0h | Readback Pin Status |
0 | rb_CLK3_EN | R | 0h | Readback Pin Status |
R86 is shown in Table 7-40.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
2 | MUXOUT_EN_OVRD | R/W | 0h | No description |
1-0 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
R90 is shown in Table 7-41.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | UNDISCLOSED | R | 0h | Program this field to 0x0. |
7 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |
6 | LOGICLK_DIV_BYP3 | R/W | 0h | This bit should be set to 1 if LOGICLK_DIV_BYP=1, 0 otherwise. |
5 | LOGICLK_DIV_BYP2 | R/W | 0h | This bit should be set to 1 if LOGICLK_DIV_BYP=1, 0 otherwise. |
4-0 | UNDISCLOSED | R/W | 0h | Program this field to 0x0. |