SNAS851 December   2023 LMX1906-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_FORCE Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
            3. 6.3.6.3.2.3 Other Pointers With SYSREF Windowing
            4. 6.3.6.3.2.4 For Glitch-Free Output
            5. 6.3.6.3.2.5 If Using SYNC Feature
          3. 6.3.6.3.3 SYNC Feature
      7. 6.3.7 Pin Mode Control
        1. 6.3.7.1 Chip Enable (CE)
        2. 6.3.7.2 Output Channel Control
        3. 6.3.7.3 Logic Output Control
        4. 6.3.7.4 SYSREF Output Control
        5. 6.3.7.5 Device Mode Selection
        6. 6.3.7.6 Divider or Multiplier Value Selection
        7. 6.3.7.7 Calibration Control Pin
        8. 6.3.7.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Applications Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plots
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Up Timing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.1 SYSREFREQ Input Configuration

The SYSREFREQ pins support single-ended or differential input in AC or DC coupling mode. The SYSREFREQ pins have an internal 50-Ω termination with capacitive ground, which acts as 100-Ω differential.

Figure 7-1 shows the generic SYSREFREQ input circuit recommendation to support all AC/DC, single-ended or differential inputs. Some of the discrete components in Figure 7-1 are just placeholder for individual input signal (single-ended or differential input) and AC or DC coupled input.

GUID-20231201-SS0I-SKND-TSHL-HWS9BHX3FSSH-low.svg Figure 7-1 SYSREFREQ Input Circuit Recommendations

The following figures show the individual circuit diagram for each configurations:

GUID-20231201-SS0I-PZ9W-4KNN-M0G7MR1WXV74-low.svgFigure 7-2 AC-Coupled Differential Input
GUID-20231201-SS0I-0ZCM-CWKD-L2M4J2L0T3FR-low.svgFigure 7-4 DC-Coupled Differential Input
GUID-20231201-SS0I-SMCB-9ZRL-CHJLBWMB4JN2-low.svgFigure 7-3 AC-Coupled, Single-Ended Input
GUID-20231201-SS0I-SKL5-BSBP-C7MS5SPHLXL1-low.svgFigure 7-5 DC-Coupled, Single-Ended Input
  1. AC coupled differential and single-ended input configurations required the resistor terminations (R2 and R3) to create the VCM at each pin and resistor values must select to maintain greater than 150-mV potential difference between pin P and pin N.
    1. As an example, to create the VCM of 1.5 V at pin P and 1.65 V at pin N, with the 2.5 V VCC, set R3 = 550 Ω and R2 = 1 kΩ
    2. For single-ended input configuration, place R6 = 50 Ω to avoid any reflection at complementary input pin.
  2. DC coupled differential and single-ended input configuration required to have the source common-mode voltage matched with the device input common mode specifications.
    1. For single-ended input configuration, keep the R1, R2, R3 and R4 resistors. This method creates the same common-mode voltage at both pins, and the resistive dividers create 75 Ω at pin P and 50 Ω thevnin's equivalent at pin N.
    2. As an example, to have the common-mode voltage of 1.35 V at each pin, set the resistive divider components values to R1 = 130 Ω, R2 = 165 Ω, R3 = 86.6 Ω and R4 = 110 Ω with the 2.5V VCC.