SNAS851 December 2023 LMX1906-SP
PRODUCTION DATA
SYSREF allows a low frequency JESD204B/C compliant signal to be produced that is reclocked to a main or LOGICLK output. The delays between the CLKOUT and SYSREF outputs are adjustable with software. The SYSREF output can be configured as a generator using the internal SYSREF divider, or as a repeater duplicating the signal on the SYSREFREQ pins. The SYSREF generator for both the main clocks and the LOGICLK output are the same.
SYSREF_MODE | DESCRIPTION |
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0 | Generator Mode Internal generator creates a continuous stream of SYSREF pulses. The SYSREFREQ pins or the SYSREFREQ_FORCE bit can be used to gate the SYSREF divider from the channels for improved noise isolation without disrupting the synchronization of the SYSREF dividers. The SYSREFREQ pins or the SYSREFREQ_FORCE bit must be high for a SYSREF output to come out. |
1 | Pulser Internal generator generates a burst of 1 - 16 pulses that is set by SYSREF_PULSE_CNT that occurs after a rising edge on the SYSREFREQ pins or after changing SYSREFREQ_FORCE bit from 0 to 1 (assuming SYSREFREQ pins to be forced to a low state). |
2 | Repeater Mode SYSREFREQ pins input are reclocked to clock outputs and then delayed in accordance to the SYSREF_DLY_BYP field before sent to the SYSREFOUT output pins. |
To operate the SYSREFREQ_FORCE bit controlled SYSREF output (Pulser) and SYNC, set the SYSREFREQ pins to low logic state externally. For example, make sure the SYSREFREQ_N pin is at a higher level (400 mV) than the SYSREFREQ_P pin and maintain the input common-mode voltage requirement.
As an example, to maintain the minimum 400-mV voltage difference for a VCC of 2.5 V, the current draw through 100 Ω will be 4 mA. In this example, keep the SYSREFREQ_P pin at 1.4-V DC, set the R2 to 350 Ω and the R1 to 175 Ω with 1.8 V at SYSREFREQ_N pin.