SNAS851 December   2023 LMX1906-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_FORCE Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
            3. 6.3.6.3.2.3 Other Pointers With SYSREF Windowing
            4. 6.3.6.3.2.4 For Glitch-Free Output
            5. 6.3.6.3.2.5 If Using SYNC Feature
          3. 6.3.6.3.3 SYNC Feature
      7. 6.3.7 Pin Mode Control
        1. 6.3.7.1 Chip Enable (CE)
        2. 6.3.7.2 Output Channel Control
        3. 6.3.7.3 Logic Output Control
        4. 6.3.7.4 SYSREF Output Control
        5. 6.3.7.5 Device Mode Selection
        6. 6.3.7.6 Divider or Multiplier Value Selection
        7. 6.3.7.7 Calibration Control Pin
        8. 6.3.7.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Applications Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plots
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Up Timing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)

SYSREF repeater mode with delay enabled is possible with LMX to LMX fanout devices by retiming the SYSREFout at different edge of IQ gen. This retiming can have the delay margin between CLKIN and SYSREFREQ inputs based on SYSREF_DLY_DIV value.

Table 6-16 shows how the total delay margin for the SYSREF windowing relates the various SYSREF settings.

Table 6-16 SYSREF Phase Adjust Settings for Retime in Repeater Mode
SYSREF_DLY_DIV POSITION CODE SELECTED DURING SYNC EDGE FOR MAX MARGIN TOTAL MARGIN IN CLKIN CYCLE SYSREFx_DLY_PHASE SYSREFx_DLY_Q SYSREFx_DLY_I

/2

Before 1st edge

I

-1, +1

"11"

0

127

After 1st edge

Qz

-1, +1

"01"

127

0

After 2nd edge

Iz

-1, +1

"00"

0

127

/4

Before 1st edge

Qz

-2, +2

"01"

127

0

After 1st edge

Iz

-2, +2

"00"

0

127

After 2nd edge

Q

-2, +2

"10"

127

0

/8

Before 1st edge

Qz

-5, +3

"01"

127

0

After 1st edge

Qz

-4, +4

"01"

127

0

After 2nd edge

Qz

-3, +5

"01"

127

0

/16

Before 1st edge

I

-9, +7

"11"

0

127

After 1st edge

I

-8, +8

"11"

0

127

After 2nd edge

I

-7, +9

"11"

0

127

Repeater retime mode is required to perform the SYSREF windowing in the initial phase to synchronize the SYSREF_DLY_DIV in multiple devices. The user can later choose the SYSREFx_DLY_PHASE, SYSREF_DLY_Q and SYSREFx_DLY_I settings for the selected edge for the SYNC.

GUID-20230821-SS0I-MD6L-G8ST-Q5R6RXJS53LC-low.svg Figure 6-10 SYSREF Windowing to Select the Edge Position for SYNC.

This configuration must set the device in SYSREF_MODE R17[1:0] value "2" (Repeater mode) and SYSREF_DLY_BPY R72[1:0] value "2" (Delay gen engaged in all modes).