SNAS851 December 2023 LMX1906-SP
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Current Consumption | |||||||
ICC | Supply Current (1) | Powered up, all outputs and SYSREF on | 1050 | mA | |||
Powered up, all outputs on, all SYSREF off | 600 | ||||||
Powered up, all outputs and SYSREF off | 265 | ||||||
Powered down(2) | 11 | ||||||
SYSREF | |||||||
fSYSREF | SYSREF output frequency | Generator mode | 200 | MHz | |||
Repeater mode | 100 | MHz | |||||
Δt | SYSREF delay step size | fCLKIN = 12.8 GHz | 3 | ps | |||
tRISE | Rise time (20% to 80%) | SYSREFOUT | 45 | ps | |||
LOGISYSREFOUT | CML | 120 | ps | ||||
LVDS | 120 | ps | |||||
tFALL | Fall time (20% to 80%) | SYSREFOUT | 45 | ps | |||
LOGISYSREFOUT | CML | 120 | ps | ||||
LVDS | 120 | ps | |||||
VOD | Differential output voltage | SYSREFOUT | 0.85 | Vpp | |||
LOGISYSREFOUT | CML | 0.4 | Vp | ||||
LVDS | 0.4 | Vp | |||||
VSYSREFCM | Common mode voltage | SYSREFOUT | CML SYSREFOUTx_PWR = 4 100 Ω Differential Load |
0.8 | V | ||
SYSREFREQ Pins | |||||||
VSYSREFIN | Voltage input range | AC differential voltage | 0.8 | 2 | Vpp | ||
VCM | Input common mode | Differential 100 Ω Termination, DC coupled Set externally |
1.2 | 1.3 | 2 | V | |
Clock Input | |||||||
fIN | Input frequency | Buffer Mode Only | 0.3 | 15(3) | GHz | ||
PIN | Input power | Single-ended power at CLKIN_P or CLKIN_N | 0 | 10 | dBm | ||
Clock Outputs | |||||||
fOUT | Output frequency | Divide-by-2 | 0.15 | 6.4 | GHz | ||
fOUT | Output frequency | Buffer Mode | 0.3 | 15(3) | |||
fOUT | Output frequency | x2, x3, x4 | 3.2 | 6.4 | |||
fOUT | Output frequency | LOGICLK output | 1 | 800 | MHz | ||
tCAL | Calibration-time | Multiplier calibration time | fIN = 3.2 GHz; x2 fSMCLK = 28 MHz |
750 | µs | ||
pOUT | Output power | Single-Ended | fCLKLOUT = 6 GHz OUTx_PWR = 7 |
6 | dBm | ||
fCLKLOUT = 12.8 GHz OUTx_PWR = 7 |
0 | ||||||
fCLKLOUT = 15 GHz OUTx_PWR = 7 |
-3 | ||||||
tRISE | Rise time (20% to 80%) | fCLKOUT = 300 MHz | 45 | ps | |||
tFALL | Fall time (20% to 80%) | fCLKOUT = 300 MHz | 45 | ps | |||
tMUTE | Output mute time | Falling edge of OE pin | 30 | µs | |||
tUNMUTE | Output unmute time | Rising edge of OE pin | 30 | µs | |||
Propagation Delay and Skew | |||||||
| tSKEW | | Magnitude of skew between outputs | TA = -55oC to +125oC | 2.5 | 10 | ps | ||
ΔtDLY/ΔT | Propagation delay variation over temp | Buffer Mode | 0.02 | 0.06 | 0.1 | ps/C | |
tDLY | Propagation delay | Buffer Mode | TA = 25°C | 180 | ps | ||
Divider Mode | 182 | ||||||
Multiplier Mode | 185 | ||||||
Noise, Jitter, and Spurs | |||||||
JCKx | Additive jitter | Additive Jitter. 12 kHz to 100 MHz integration bandwidth. | Buffer Mode | 5 | fs, rms | ||
x2 Multiplier | 16 | ||||||
x3 Multiplier | 21 | ||||||
x4 Multiplier | 26 | ||||||
Flicker | 1/f flicker noise | Slew Rate > 8 V/ns, fCLK=6 GHz | Buffer Mode | –155 | dBc/Hz | ||
NFL | Noise Floor | fOUT = 6 GHz; fOffset = 100 MHz | Buffer Mode | –159 | dBc/Hz | ||
NFL | Divide-by-2 | –158.5 | |||||
NFL | Multiplier (x2,x3,x4) | –159.5 | |||||
NFL | Noise Floor | LOGICLK output, 300 MHz | CML | –150.5 | dBc/Hz | ||
NFL | LVDS | –151.5 | |||||
H2 | Second harmonic | fOUT = 6 GHz (differential), Buffer Mode | –25 | dBc | |||
fOUT = 6 GHz (single-ended), Buffer Mode | –13 | ||||||
fOUT = 6 GHz, single-ended, Divide by 2 | –16 | ||||||
H1/2 | Input clock leakage spur | fOUT = 6 GHz (single-ended) | x2 (fSPUR = 3 GHz) | –40 | dBc | ||
H1/3 | x3 (fSPUR = 2 GHz) | –50 | |||||
H1/4 | x4 (fSPUR = 1.5 GHz) | –54 | dBc | ||||
ISPUR | LOGICLK to CLKOUT | fSPUR = 300 MHz (differential) | –70 | dBc | |||
Digital Interface (SCK, SDI, CS#, MUXOUT, CLKx_EN, MUXSELx, PWRSELx, DIVSELx, LOGIC_EN, SYSREF_EN, CAL,CE) | |||||||
VIH | High-level input voltage | SCK, SDI, CS# | 1.4 | 3.3 | V | ||
High-level input voltage | CLKx_EN, MUXSELx, PWRSELx, DIVSELx,LOGIC_EN, SYSREF_EN, CAL, CE | 1.4 | 3.3 | V | |||
VIL | Low-level input voltage | SCK, SDI, CS# | 0 | 0.4 | V | ||
Low-level input voltage | CLKx_EN, MUXSELx, PWRSELx, DIVSELx, LOGIC_EN, SYSREF_EN, CAL, CE | 0 | 0.4 | V | |||
IIH | High-level input current | SCK, SDI, CS# | –42 | 42 | µA | ||
High-level input current | CLKx_EN, MUXSELx, PWRSELx, DIVSELx, LOGIC_EN, SYSREF_EN, CAL, CE | –42 | 42 | µA | |||
IIL | Low-level input current | SCK, SDI, CS# | –25 | 25 | µA | ||
Low-level input current | CLKx_EN, MUXSELx, PWRSELx, DIVSELx, LOGIC_EN, SYSREF_EN, CAL, CE | –25 | 25 | µA | |||
VOH | High-level output voltage | MUXOUT | IOH = 5 mA | 1.4 | 2.2 | V | |
High-level output voltage | IOH = 0.1 mA | 2.2 | 2.5 | V | |||
VOL | Low-level output voltage | MUXOUT | IOL = 5 mA | 0.45 | V |