8.3.5.1 High Frequency Input Pins, FinRF and FinIF

It is generally recommended that the VCO output go through a resistive pad and then through a DC-blocking capacitor before it gets to these high frequency input pins. If the trace length is sufficiently short (< 1/10th of a wavelength), then the pad may not be necessary, but a series resistor of about 39 Ω is still recommended to isolate the PLL from the VCO. The DC-blocking capacitor should be chosen at least to be 27 pF. It may turn out that the frequency is above the self-resonant frequency of the capacitor, but because the input impedance of the PLL tends to be capacitive, it actually is a benefit to exceed the tune frequency. The pad and the DC-blocking capacitor should be placed as close to the PLL as possible

8.3.5.2 Complementary High Frequency Pin, FinRF*

These inputs may be used to drive the PLL differentially, but it is very common to drive the PLL in a single ended fashion. A shunt capacitor should be placed at the FinRF* pin. The value of this capacitor should be chosen such that the impedance, including the ESR of the capacitor, is as close to an AC short as possible at the operating frequency of the PLL. 100 pF is a typical value.

Table 6. Programmable Lock Detect Settings

Table 7. Fastlock/Cycle Slip Reduction Usage

8.3.7.1 Cycle Slip Reduction (CSR)

Cycle slip reduction works by reducing the comparison frequency during frequency acquisition while keeping the same loop bandwidth, thereby reducing the ratio of the comparison frequency to the loop bandwidth. In cases where the ratio of the comparison frequency exceeds about 100 times the loop bandwidth, cycle slipping can occur and significantly degrade lock times. The greater this ratio, the greater the benefit of CSR. This is typically the case of high comparison frequencies. In circumstances where there is not a problem with cycle slipping, CSR provides no benefit. There is a glitch when CSR is disengaged, but because CSR should be disengaged long before the PLL is actually in lock, this glitch is not an issue. A good rule of thumb for CSR disengagement is to do this at the peak time of the transient response. Because this time is typically much sooner than Fastlock should be disengaged, it does not make sense to use CSR and Fastlock in combination.

8.3.7.2 Fastlock

Fastlock works by increasing the loop bandwidth only during frequency acquisition. In circumstances where the comparison frequency is less than or equal to 2 MHz, Fastlock may provide a benefit beyond what CSR can offer. Because Fastlock also reduces the ratio of the comparison frequency to the loop bandwidth, it may provide a significant benefit in cases where the comparison frequency is above 2 MHz. However, CSR can usually provide an equal or larger benefit in these cases, and can be implemented without using an additional resistor. The reason for this restriction on frequency is that Fastlock has a glitch when it is disengaged. As the time of engagement for Fastlock decreases and becomes on the order of the fast lock time, this glitch grows and limits the benefits of Fastlock. This effect becomes worse at higher comparison frequencies. There is always the option of reducing the comparison frequency at the expense of phase noise to satisfy this constraint on comparison frequency. Despite this glitch, there is still a net improvement in lock time using Fastlock in these circumstances. When using Fastlock, it is also recommended that the steady-state charge pump state be 4X or less. Also, Fastlock was originally intended only for second order filters, so when implementing it with higher order filters, the third and fourth poles can not be too close in, or it will not be possible to keep the loop filter well optimized when the higher charge pump current and Fastlock resistor are engaged.

8.3.7.3 Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping

Once it is decided that CSR is to be used, the cycle slip reduction factor needs to be chosen. The available factors are 1/2, 1/4, and 1/16. To preserve the same loop characteristics, TI recommends that Equation 4 be satisfied:

To satisfy this constraint, the maximum charge pump current in steady-state is 8X for a CSR of 1/2, 4X for a CSR of 1/4, and 1X for a CSR of 1/16. Because the PLL phase noise is better for higher charge pump currents, it makes sense to choose CSR only as large as necessary to prevent cycle slipping. Choosing it larger than this will not improve lock time, and will result in worse phase noise.

Consider an example where the desired loop bandwidth in steady-state is 100 kHz and the comparison frequency is 20 MHz. This yields a ratio of 200. Cycle slipping may be present, but would not be too severe if it was there. If a CSR factor of 1/2 is used, this would reduce the ratio to 100 during frequency acquisition, which is probably sufficient. A charge pump current of 8X could be used in steady-state, and a factor of 16X could be used during frequency acquisition. This yields a ratio of 1/2, which is equal to the CSR factor and this satisfies the above constraint. In this circumstance, it could also be decided to just use 16X charge pump current all the time, because it would probably have better phase noise, and the degradation in lock time would not be too severe.

8.3.7.4 Using Fastlock to Improve Lock Times

Figure 23. Loop Filter with Fastlock Resistor

Once it is decided that Fastlock is to be used, the loop bandwidth multiplier, K, is needed to determine the theoretical impact of Fastlock on the loop bandwidth and the resistor value, R2p, that is switched in parallel during Fastlock. This ratio is calculated in Equation 5:

The above table shows how to calculate the Fastlock resistor and theoretical lock time improvement, once the ratio , K, is known. This all assumes a second order filter (not counting the pole at 0 Hz). However, it is generally recommended that the loop filter order be one greater than the order of the delta sigma modulator, which means that a second order filter is never recommended. In this case, the value for R2p is typically about 80% of what it would be for a second order filter. Because the Fastlock disengagement glitch gets larger and it is harder to keep the loop filter optimized as the K value becomes larger, designing for the largest possible value for K usually, but not always yields the best improvement in lock time. To get a more accurate estimate requires more simulation tools, or trial and error.

8.3.7.5 Capacitor Dielectric Considerations for Lock Time

The LMX2486 has a high fractional modulus and high charge pump gain for the lowest possible phase noise. One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop filter to become larger in value. For larger capacitor values, it is common to have a trade-off between capacitor dielectric quality and physical size. Using film capacitors or NPO/COG capacitors yields the best possible lock times, where as using X7R or Z5R capacitors can increase lock time by 0 – 500%. However, it is a general tendency that designs that use a higher compare frequency tend to be less sensitive to the effects of capacitor dielectrics. Although the use of lesser quality dielectric capacitors may be unavoidable in many circumstances, allowing a larger footprint for the loop filter capacitors, using a lower charge pump current, and reducing the fractional modulus are all ways to reduce capacitor values. Capacitor dielectrics have very little impact on phase noise and spurs.

Table 9. Powerdown Modes

Table 10. Programmable Register Structure

8.5.1.1 Register Location Truth Table

The control bits CTL [3:0] decode the internal register address. The table below shows how the control bits are mapped to the target control register.

8.5.1.2 Control Register Content Map

Because the LMX2486 registers are complicated, they are organized into two groups, basic and advanced. The first four registers are basic registers that contain critical information necessary for the PLL to achieve lock. The last 5 registers are for features that optimize spur, phase noise, and lock time performance. The next page shows these registers.

Although it is highly recommended that the user eventually take advantage of all the modes of the LMX2486, the quick start register map is shown in order for the user to get the part up and running quickly using only those bits critical for basic functionality. The following default conditions for this programming state are a third order delta-sigma modulator in 12-bit mode with strong dithering and no Fastlock.

The complete register map shows all the functionality of all registers, including the last five.

Table 14. R0 Register

8.6.1.1 RF_FN[11:0] -- Fractional Numerator for RF PLL

Refer to Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], Access[1] } for a more detailed description of this control word.

8.6.1.2 RF_N[10:0] -- RF N Counter Value

The RF N counter contains an 16/17/20/21 and a 32/33/36/37 prescaler. The N counter value can be calculated as follows:

N = RF_P·RF_C + 4·RF_B + RF_A

RF_C ≥Max{RF_A, RF_B} , for N-2^FM-1 ... N+2^FM is a necessary condition. This rule is slightly modified in the case where the RF_B counter has an unused bit, where this extra bit is used by the delta-sigma modulator for the purposes of modulation. Consult the tables below for valid operating ranges for each prescaler.

Table 17. R1 Register

8.6.2.1 RF_FD[11:0] -- RF PLL Fractional Denominator

The function of these bits are described in Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], Access[1]}.

8.6.2.2 RF_R [5:0] -- RF R Divider Value

The RF R Counter value is determined by this control word.

8.6.2.3 RF_P -- RF Prescaler bit

The prescaler used is determined by this bit.

8.6.2.4 RF_PD -- RF Power Down Control Bit

When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and the RF Charge pump is set to a TRI-STATE mode. The CE pin and ATPU bit also control power down functions, and will override the RF_PD bit. The order of precedence is as follows. First, if the CE pin is LOW, then the PLL will be powered down. Provided this is not the case, the PLL will be powered up if the ATPU bit says to do so, regardless of the state of the RF_PD bit. After the CE pin and the ATPU bit are considered, then the RF_PD bit then takes control of the power down function for the RF PLL.

Table 20. R2 Register

8.6.3.1 IF_N[18:0] -- IF N Divider Value

8.6.3.2 IF_PD -- IF Power Down Bit

When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the output of the IF PLL charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written to, the IF_PD will be reset to 0 and the IF PLL will be powered up. If the CE pin is held low, the IF PLL will be powered down, overriding the IF_PD bit.

Table 23. R3 Register

8.6.4.1 IF_R[11:0] -- IF R Divider Value

For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for IF_R is 3.

8.6.4.2 RF_CPG -- RF PLL Charge Pump Gain

This is used to control the magnitude of the RF PLL charge pump in steady-state operation.

8.6.4.3 Access -- Register Access Word

It is mandatory that the first 5 registers R0-R4 be programmed. The programming of registers R5-R7 is optional. The ACCESS[3:0] bits determine which additional registers must be programmed. Any one of these registers can be individually programmed. According to the table below, when the state of a register is in default mode, all the bits in that register are forced to a default state and it is not necessary to program this register. When the register is programmable, it needs to be programmed through the MICROWIRE. Using this register access technique, the programming required is reduced up to 50%.

The default conditions the registers is shown in Table 27:

This corresponds to the bit settings in Table 28.

Table 29. R4 Register

8.6.5.1 MUX[3:0] Frequency Out and Lock Detect MUX

These bits determine the output state of the Ftest/LD pin.

8.6.5.2 IF_P -- IF Prescaler

When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.

8.6.5.3 RF_CPP -- RF PLL Charge Pump Polarity

8.6.5.4 IF_CPP -- IF PLL Charge Pump Polarity

For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a negative phase detector polarity.

8.6.5.5 OSC_OUT Oscillator Output Buffer Enable

8.6.5.6 OSC2X -- Oscillator Doubler Enable

When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF R counters is equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency presented to the RF R counter is doubled. Phase noise added by the doubler is negligible.

8.6.5.7 FM[1:0] -- Fractional Mode

Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the loop filter should be at least one greater than the order of the delta-sigma modulator to allow for sufficient roll-off.

8.6.5.8 DITH[1:0] -- Dithering Control

Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional spurs, but can also give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific. Enabling the dithering may also increase the phase noise. In most cases where the fractional numerator is zero, dithering usually degrades performance.

Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often occurs when the loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends not to impact the main fractional spurs much, but has a much larger impact on the sub-fractional spurs. If it is decided that dithering will be used, best results will be obtained when the fractional denominator is at least 1000.

8.6.5.9 ATPU -- PLL Automatic Power Up

When this bit is set to 1, both the RF and IF PLL power up when the R0 register is written to. When the R0 register is written to, the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case is when the CE pin is low. In this case, the ATPU function is disabled.

Table 38. R5 Register

8.6.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], Access[1] }

In the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12] bits become do not care bits. When the ACCESS[1] bit is set to 1, the part operates in 22-bit mode and the fractional numerator is expanded from 12 to 22-bits.

8.6.6.2 Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], Access[1]}

In the case that the ACCESS[1] bit is 0, then the part is operates in the 12-bit fractional mode, and the RF_FD[21:12] bits become do not care bits. When the ACCESS[1] is set to 1, the part operates in 22-bit mode and the fractional denominator is expanded from 12 to 22-bits.

Table 41. R6 Register

8.6.7.1 RF_TOC -- RF Time-Out Counter and Control for FLoutRF Pin

The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as the function of the FLoutRF output pin. When this word is set to a value between 0 and 3, the RF Fastlock circuitry is disabled and the FLoutRF pin operates as a general-purpose CMOS TRI-STATE I/O. When RF_TOC is set to a value between 4 and 16383, the RF Fastlock mode is enabled and the FLoutRF pin is used as the RF Fastlock output pin. The value programmed into the RF_TOC[13:0] word represents two times the number of phase detector comparison cycles the RF synthesizer will spend in the Fastlock state.

8.6.7.2 RF_CPF -- RF PLL Fastlock Charge Pump Current

Specify the charge pump current for the Fastlock operation mode for the RF PLL.

8.6.7.3 CSR[1:0] -- RF Cycle Slip Reduction

CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence of phase detector cycle slips.

Table 45. R7 Register

8.6.8.1 DIV4 -- RF Digital Lock Detect Divide By 4

Because the digital lock detect function is based on a phase error, it becomes more difficult to detect a locked condition for larger comparison frequencies. When this bit is enabled, it subdivides the RF PLL comparison frequency (it does not apply to the IF comparison frequency) presented to the digital lock detect circuitry by 4. This enables this circuitry to work at higher comparison frequencies. TI recommends that this bit be enabled whenever the comparison frequency exceeds 20 MHz and RF digital lock detect is being used.

8.6.8.2 IF_RST -- IF PLL Counter Reset

When this bit is enabled, the IF PLL N and R counters are reset, and the charge pump is put in a TRI-STATE condition. This feature should be disabled for normal operation.

8.6.8.3 RF_RST -- RF PLL Counter Reset

When this bit is enabled, the RF PLL N and R counters are reset and the charge pump is put in a TRI-STATE condition. This feature should be disabled for normal operation. This feature should be disabled for normal operation.

8.6.8.4 RF_TRI -- RF Charge Pump TRI-STATE

When this bit is enabled, the RF PLL charge pump is put in a TRI-STATE condition, but the counters are not reset. This feature is typically disabled for normal operation.

8.6.8.5 IF_TRI -- IF Charge Pump TRI-STATE

When this bit is enabled, the IF PLL charge pump is put in a TRI-STATE condition, but the counters are not reset. This feature is typically disabled for normal operation.