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  • LMX2487E 7.5-GHz, High-Performance, Delta-Sigma Low-Power Dual PLLatinum Frequency Synthesizers With 3-GHz Integer PLL

    • SNAS404B May   2007  – January 2016 LMX2487E

      PRODUCTION DATA.  

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  • LMX2487E 7.5-GHz, High-Performance, Delta-Sigma Low-Power Dual PLLatinum Frequency Synthesizers With 3-GHz Integer PLL
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Sensitivity
      2. 6.7.2 FinRF Input Impedance
      3. 6.7.3 FinIF Input Impedance
      4. 6.7.4 OSCin Input Impedance
      5. 6.7.5 Currents
  7. 7 Parameter Measurement Information
    1. 7.1 Bench Test Set-Ups
      1. 7.1.1 Charge Pump Current Measurement
      2. 7.1.2 Charge Pump Current Specification Definitions
        1. 7.1.2.1 Charge Pump Output Current Variation vs Charge Pump Output Voltage
        2. 7.1.2.2 Charge Pump Output Current Variation vs Temperature
      3. 7.1.3 Sensitivity Measurement
      4. 7.1.4 Input Impedance Measurement
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TCXO, Oscillator Buffer, and R Counter
      2. 8.3.2 Phase Detector
      3. 8.3.3 Charge Pump
      4. 8.3.4 Loop Filter
      5. 8.3.5 N Counters and High Frequency Input Pins
        1. 8.3.5.1 High Frequency Input Pins, FinRF and FinIF
        2. 8.3.5.2 Complementary High Frequency Pin, FinRF*
      6. 8.3.6 Digital Lock Detect Operation
      7. 8.3.7 Cycle Slip Reduction and Fastlock
        1. 8.3.7.1 Cycle Slip Reduction (CSR)
        2. 8.3.7.2 Fastlock
        3. 8.3.7.3 Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping
        4. 8.3.7.4 Using Fastlock to Improve Lock Times
        5. 8.3.7.5 Capacitor Dielectric Considerations for Lock Time
      8. 8.3.8 Fractional Spur and Phase Noise Controls
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Pins, Power-Down, and Power-Up Modes
    5. 8.5 Programming
      1. 8.5.1 General Programming Information
        1. 8.5.1.1 Register Location Truth Table
        2. 8.5.1.2 Control Register Content Map
    6. 8.6 Register Maps
      1. 8.6.1 R0 Register
        1. 8.6.1.1 RF_FN[11:0] - Fractional Numerator for RF PLL
        2. 8.6.1.2 RF_N[10:0] - RF N Counter Value
      2. 8.6.2 R1 REGISTER
        1. 8.6.2.1 RF_FD[11:0] - RF PLL Fractional Denominator
        2. 8.6.2.2 RF_R [5:0] - RF R Divider Value
        3. 8.6.2.3 RF_P - RF Prescaler bit
        4. 8.6.2.4 RF_PD - RF Power-Down Control Bit
      3. 8.6.3 R2 Register
        1. 8.6.3.1 IF_N[18:0] - IF N Divider Value
        2. 8.6.3.2 IF_PD - IF Power Down Bit
      4. 8.6.4 R3 Register
        1. 8.6.4.1 IF_R[11:0] - IF R Divider Value
        2. 8.6.4.2 RF_CPG - RF PLL Charge Pump Gain
        3. 8.6.4.3 ACCESS - Register Access Word
      5. 8.6.5 R4 Register
        1. 8.6.5.1 MUX[3:0] Frequency Out and Lock Detect MUX
        2. 8.6.5.2 IF_P - IF Prescaler
        3. 8.6.5.3 RF_CPP - RF PLL Charge Pump Polarity
        4. 8.6.5.4 IF_CPP - IF PLL Charge Pump Polarity
        5. 8.6.5.5 OSC_OUT Oscillator Output Buffer Enable
        6. 8.6.5.6 OSC2X - Oscillator Doubler Enable
        7. 8.6.5.7 FM[1:0] - Fractional Mode
        8. 8.6.5.8 DITH[1:0] - Dithering Control
        9. 8.6.5.9 ATPU - PLL Automatic Power Up
      6. 8.6.6 R5 Register
        1. 8.6.6.1 Fractional Numerator Determination [ RF_FN[21:12], RF_FN[11:0], Access[1] ]
        2. 8.6.6.2 Fractional Denominator Determination [ RF_FD[21:12], RF_FD[11:0], Access[1]]
      7. 8.6.7 R6 Register
        1. 8.6.7.1 RF_TOC - RF Time Out Counter and Control for FLoutRF Pin
        2. 8.6.7.2 RF_CPF - RF PLL Fastlock Charge Pump Current
        3. 8.6.7.3 CSR[1:0] - RF Cycle Slip Reduction
      8. 8.6.8 R7 Register
        1. 8.6.8.1 DIV4 - RF Digital Lock Detect Divide By 4
        2. 8.6.8.2 IF_RST - IF PLL Counter Reset
        3. 8.6.8.3 RF_RST - RF PLL Counter Reset
        4. 8.6.8.4 RF_TRI - RF Charge Pump Tri-State
        5. 8.6.8.5 IF_TRI - IF Charge Pump Tri-State
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RTW|24
    • MPQF167C
Thermal pad, mechanical data (Package|Pins)
  • RTW|24
    • QFND450A
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  • snas404b_pm
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DATA SHEET

LMX2487E 7.5-GHz, High-Performance, Delta-Sigma Low-Power Dual PLLatinum Frequency Synthesizers With 3-GHz Integer PLL

1 Features

  • Quadruple Modulus Prescaler for Lower Divids
    • RF PLL: 16/17/20/21 or 32/33/36/37
    • IF PLL: 8/9 or 16/17
  • Advanced Delta Sigma Fractional Compensation
    • 12-Bit or 22-Bit Selectable Fractional Modulus
    • Up to 4th Order Programmable Delta-Sigma Modulator
  • Features for Improved Lock Time
    • Fastlock / Cycle Slip Reduction that Requires Single-Word Write
    • Integrated Time-Out Counter
  • Wide Operating Range
    • LMX2487E RF PLL: 3.0 GHz to 7.5 GHz
  • Useful Features
    • Digital Lock Detect Output
    • Hardware and Software Power-Down Control
    • On-Chip Crystal Reference Frequency Doubler
    • RF Phase Comparison Frequency Up to 50 MHz
    • 2.5-V to 3.6-V Operation With ICC = 8.5 mA at 3.0 V

2 Applications

  • Cellular Phones and Base Stations
  • Direct Digital Modulation Applications
  • Satellite and Cable TV Tuners
  • WLAN Standards

3 Description

The LMX2487E device is a low power, high performance delta-sigma fractional-N PLL with an auxiliary integer-N PLL. It is fabricated using TI’s advanced process.

With delta-sigma architecture, fractional spurs at lower offset frequencies are pushed to higher frequencies outside the loop bandwidth. The ability to push close in spur and phase noise energy to higher frequencies is a direct function of the modulator order. Unlike analog compensation, the digital feedback technique used in the LMX2487E is highly resistant to changes in temperature and variations in wafer processing. The LMX2487E delta-sigma modulator is programmable up to fourth order, which allows the designer to select the optimum modulator order to fit the phase noise, spur, and lock time requirements of the system.

Serial data for programming the LMX2487E is transferred through a three-line, high-speed (20-MHz) MICROWIRE interface. The LMX2487E offers fine frequency resolution, low spurs, fast programming speed, and a single-word write to change the frequency. This makes it ideal for direct digital modulation applications, where the N-counter is directly modulated with information. The LMX2487E is available in a 24-lead 4.0 × 4.0 × 0.8 mm WQFN package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMX2487E WQFN (24) 4.00 mm × 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

LMX2487E 20154701.gif

4 Revision History

Changes from A Revision (March 2013) to B Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from * Revision (March 2013) to A Revision

  • Changed layout of National Data Sheet to TI formatGo

5 Pin Configuration and Functions

RTW Package
24-Pin WQFN
Top View
LMX2487E 20087722.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
0 GND — Ground Substrate. This is on the bottom of the package and must be grounded.
1 CPoutRF O RF PLL charge pump output.
2 GND — RF PLL analog ground.
3 VddRF1 — RF PLL analog power supply.
4 FinRF I RF PLL high-frequency input pin.
5 FinRF* I RF PLL complementary high-frequency input pin. Shunt to ground with a 100-pF capacitor.
6 LE I MICROWIRE Load Enable. High-impedance CMOS input. Data stored in the shift registers is loaded into the internal latches when LE goes HIGH
7 DATA I MICROWIRE Data. High-impedance binary serial data input.
8 CLK I MICROWIRE Clock. High-impedance CMOS Clock input. Data for the various counters is clocked into the 24-bit shift register on the rising edge
9 VddRF2 — Power supply for RF PLL digital circuitry.
10 CE I Chip Enable control pin. Must be pulled high for normal operation.
11 VddRF5 I Power supply for RF PLL digital circuitry.
12 Ftest/LD O Test frequency output / Lock Detect.
13 FinIF I IF PLL high-frequency input pin.
14 VddIF1 — IF PLL analog power supply.
15 GND — IF PLL digital ground.
16 CPoutIF O IF PLL charge pump output
17 VddIF2 — IF PLL power supply.
18 OSCout O Buffered output of the OSCin signal.
19 ENOSC I Oscillator enable. When this is set to high, the OSCout pin is enabled regardless of the state of other pins or register bits.
20 OSCin I Reference Input.
21 NC I This pin must be left open.
22 VddRF3 — Power supply for RF PLL digital circuitry.
23 FLoutRF O RF PLL Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
24 VddRF4 — RF PLL analog power supply.

6 Specifications

6.1 Absolute Maximum Ratings

See (1).
MIN MAX UNIT
VCC Power supply voltage –0.3 4.25 V
Vi Voltage on any pin with GND = 0 V –0.3 VCC + 0.3 V
TL Lead temperature (Solder 4 sec.) 260 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge(1) Human-body model (HBM) ±2000 V
Charged-device model (CDM) ±750
Machine model (MM) ±200
(1) This is a high performance RF device is ESD-sensitive. Handling and assembly of this device should be done at an ESD free workstation.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Power supply voltage (1) 2.5 3 3.6 V
TA Operating temperature -40 25 85 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. The voltage at all the power supply pins of VddRF1, VddRF2, VddRF3, VddRF4, VddRF5, VddIF1 and VddIF2 must be the same. VCC will be used to refer to the voltage at these pins and ICC will be used to refer to the sum of all currents through all these power pins.

6.4 Thermal Information

THERMAL METRIC(1) LMX2485, LMX2485E UNIT
RTW (WQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 47.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 43 °C/W
RθJB Junction-to-board thermal resistance 24 °C/W
ψJT Junction-to-top characterization parameter 0.8 °C/W
ψJB Junction-to-board characterization parameter 24 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

(VCC = 3.0V; -40°C ≤ TA ≤ +85°C unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC PARAMETERS
ICCRF Power supply current, RF synthesizer IF PLL OFF
RF PLL ON
Charge pump TRI-STATE		 5.7 mA
ICCIF Power supply current, IF synthesizer IF PLL ON
RF PLL OFF
Charge pump TRI-STATE		 2.5 mA
ICCTOTAL Power supply current, entire synthesizer IF PLL ON
RF PLL ON
Charge pump TRI-STATE		 8.5 mA
ICCPD Power-down current CE = ENOSC = 0 V
CLK, DATA, LE = 0 V		 < 1 µA
RF SYNTHESIZER PARAMETERS
fFinRF Operating frequency LMX2487E RF_P = 16 3000 4000 MHz
RF_P = 32 3000 7500
pFinRF Input sensitivity 3-6 GHz -10 0 dBm
6-7.5 GHz -5 5
fCOMP Phase detector frequency(1) 50 MHz
ICPoutRFSRCE RF charge pump source current(2) RF_CPG = 0
VCPoutRF = VCC/2		 95 µA
RF_CPG = 1
VCPoutRF = VCC/2		 190 µA
... ... µA
RF_CPG = 15
VCPoutRF = VCC/2		 1520 µA
ICPoutRFSINK RF charge pump sink current(2) RF_CPG = 0
VCPoutRF = VCC/2		 –95 µA
RF_CPG = 1
VCPoutRF = VCC/2		 –190 µA
... ... µA
RF_CPG = 15
VCPoutRF = VCC/2		 –1520 µA
ICPoutRFTRI RF charge pump TRI-STATE current magnitude 0.5 ≤ VCPoutRF ≤ VCC -0.5 2 10 nA
| ICPoutRF%MIS | Magnitude of RF CP sink vs CP source mismatch VCPoutRF = VCC/2
TA = 25°C		 RF_CPG > 2 3% 10%
RF_CPG ≤ 2 3% 13%
| ICPoutRF%V | Magnitude of RF CP current vs CP voltage 0.5 ≤ VCPoutRF ≤ VCC -0.5
TA = 25°C		 2% 8%
| ICPoutRF%T | Magnitude of RF CP current vs temperature VCPoutRF = VCC/2 4%
IF SYNTHESIZER PARAMETERS
fFinIF Operating frequency IF_P = 8 250 2000 MHz
IF_P = 16 250 3000
pFinIF IF input sensitivity –10 5 dBm
fCOMP Phase detector frequency 10 MHz
ICPoutIFSRCE IF charge pump source current VCPoutIF = VCC/2 3.5 mA
ICPoutIFSINK IF charge pump sink current VCPoutIF = VCC/2 –3.5 mA
ICPoutIFTRI IF charge pump TRI-STATE current magnitude 0.5 ≤ VCPoutIF ≤ VCC RF – 0.5 2 10 nA
| ICPoutIF%MIS | Magnitude of IF CP sink vs CP source mismatch VCPoutIF = VCC/2
TA = 25°C		 1% 8%
| ICPoutIF%V | Magnitude of IF CP current vs CP voltage 0.5 ≤ VCPoutIF ≤ VCC – 0.5
TA = 25°C		 4% 10%
| ICPoutIF%TEMP Magnitude of IF CP current vs temperature VCPoutIF = VCC/2 4%
OSCILLATOR PARAMETERS
fOSCin Oscillator operating frequency OSC2X = 0 5 110 MHz
OSC2X = 1 5 20 MHz
vOSCin Oscillator input sensitivity 0.5 VCC VP-P
IOSCin Oscillator input current –100 100 µA
SPURS
Spurs in band(3) -55 dBc
PHASE NOISE
LF1HzRF RF synthesizer normalized phase noise contribution(4) RF_CPG = 0 –202 dBc/Hz
RF_CPG = 1 –204
RF_CPG = 3 –206
RF_CPG = 7 –210
RF_CPG = 15 –210
LF1HzIF IF synthesizer normalized phase noise contribution –209 dBc/Hz
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
VIH High-level input voltage 1.6 VCC V
VIL Low-level input voltage 0.4 V
IIH High-level input current VIH = VCC –1 1 µA
IIL Low-level input current VIL = 0 V –1 1 µA
VOH High-level output voltage IOH = –500 µA VCC – 0.4 V
VOL Low-level output voltage IOL = 500 µA 0.4 V
(1) For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required.
(2) Refer to table in RF_CPG – RF PLL Charge Pump Gain for complete listing of charge pump currents.
(3) In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one. The spur offset frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth must be sufficiently wide to negate the impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency = 20 MHz, RF_CPG = 7, DITH = 0, VCO Frequency = 3 GHz, and a 4th Order Modulator (FM = 0). These are relatively consistent over tuning range.
(4) Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(fCOMP) where L(f) is defined as the single side band phase noise measured at an offset frequency, f, in a 1-Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. Measurement conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for RF_CPG = 7, Fraction = 1/2000, Comparison Frequency = 20 MHz, FM = 0, DITH = 0, VCO Frequency = 3 GHz.

6.6 Timing Requirements

MIN NOM MAX UNIT
MICROWIRE INTERFACE TIMING
tCS Data to clock set-up time See Figure 1 25 ns
tCH Data to clock hold time See Figure 1 8 ns
tCWH Clock pulse width high See Figure 1 25 ns
tCWL Clock pulse width low See Figure 1 25 ns
tES Clock to load enable set-up time See Figure 1 25 ns
tEW Load enable pulse width See Figure 1 25 ns
LMX2487E 20087775.gif Figure 1. MICROWIRE Input Timing Diagram

6.7 Typical Characteristics

6.7.1 Sensitivity

Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics.
LMX2487E 20154745.gif
TA = 25°C, RF_P = 32
Figure 2. RF PLL Fin Sensitivity
LMX2487E 20154747.gif
TA = 25°C, IF_P = 16
Figure 4. IF PLL Fin Sensitivity
LMX2487E 20154749.gif
TA = 25°C, OSC_2X = 0
Figure 6. OSCin Sensitivity
LMX2487E 20154773.gif
TA = 25°C, OSC_2X =1
Figure 8. OSCin Sensitivity
LMX2487E 30013946.gif
VCC = 3 V, RF_P = 32
Figure 3. RF PLL Fin Sensitivity
LMX2487E 20154748.gif
VCC = 3 V, IF_P = 16
Figure 5. IF PLL Fin Sensitivity
LMX2487E 20154756.gif
VCC = 3 V, OSC_2X = 0
Figure 7. OSCin Sensitivity
LMX2487E 20154774.gif
VCC = 3 V, OSC_2X = 1
Figure 9. OSCin Sensitivity

6.7.2 FinRF Input Impedance

Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics.
LMX2487E 30013968.gif Figure 10. FinRF Input Impedance

Table 1. RF PLL Input Impedance

FinRF INPUT IMPEDANCE
FREQUENCY (MHz) REAL (Ω) IMAGINARY (Ω)
3000 39 –94
3200 37 –86
3400 33 –78
3600 30 –72
3800 28 –69
4000 26 –66
4250 24 –63
4500 23 –60
4750 22 –57
5000 20 –54
5250 19 –50
5500 18 –49
5750 17 –47
6000 17 –45
6250 16 –44
6500 16 –42
6750 16 –40
7000 16 –39
7250 16 –37
7500 16 –35
7750 17 –33
8000 17 –30
8250 16 –27

6.7.3 FinIF Input Impedance

Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics.
LMX2487E 20154754.gif Figure 11. FinIF Input Impedance

Table 2. IF PLL Input Impedance

FinIF INPUT IMPEDANCE
FREQUENCY (MHz) REAL (Ω) IMAGINARY (Ω)
100 508 –233
150 456 –215
200 420 –206
250 403 –205
300 370 –207
400 344 –215
500 207 –223
600 274 –225
700 242 –225
800 242 –225
900 214 –222
1000 171 –208
1200 137 –191
1400 112 –176
1600 91 –158
1800 76 –139
2000 62 –122
2200 51 –105
2300 46 –96
2400 42 –88
2600 37 –74
2800 29 –63
3000 25 –54

6.7.4 OSCin Input Impedance

Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics.
LMX2487E 20154755.gif Figure 12. OSCin Input Impedance

Table 3. OSCin Input Impedance

FREQUENCY (MHz) POWERED UP POWERED DOWN
REAL IMAGINARY MAGNITUDE REAL IMAGINARY MAGNITUDE
5 1730 –3779 4157 392 –8137 8146
10 846 –2236 2391 155 –4487 4490
20 466 –1196 1284 107 –2215 2217
30 351 –863 932 166 –1495 –1504
40 316 –672 742 182 –1144 1158
50 278 –566 631 155 –912 925
60 261 –481 547 153 –758 774
70 252 –425 494 154 –652 669
80 239 –388 456 147 –576 595
90 234 –358 428 145 –518 538
100 230 –337 407 140 –471 492
110 225 –321 392 138 –436 458
120 219 –309 379 133 –402 123
130 214 –295 364 133 –374 397
140 208 –285 353 132 –349 373
150 207 –279 348 133 –329 355

6.7.5 Currents

Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in Electrical Characteristics.
LMX2487E 30013959.gif
CE = High
Figure 13. Power Supply Current
LMX2487E 20154765.gif
VCC = 3 V
Figure 15. IF PLL Charge Pump Current
LMX2487E 20154763.gif
VCC = 3 V
Figure 17. Charge Pump Leakage IF PLL
LMX2487E 30013967.gif
VCC = 3 V
Figure 14. RF PLL Charge Pump Current
LMX2487E 20154764.gif
VCC = 3 V
Figure 16. Charge Pump Leakage RF PLL

 
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