SNAS252S October   2005  – December 2014 LMX2531

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 MICROWIRE Timing Requirements
    7. 6.7 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference Oscillator Input
      2. 7.3.2 R Divider
      3. 7.3.3 Phase Detector and Charge Pump
      4. 7.3.4 N Divider and Fractional Circuitry
      5. 7.3.5 Partially Integrated Loop Filter
      6. 7.3.6 Low Noise, Fully Integrated VCO
      7. 7.3.7 Programmable VCO Divider
      8. 7.3.8 Serial Data Timing Requirements
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 General Programming Information
        1. 7.6.1.1  Initialization Sequence
        2. 7.6.1.2  Complete Register Content Map
        3. 7.6.1.3  Register R0
          1. 7.6.1.3.1 NUM[10:0] and NUM[21:12] -- Fractional Numerator
          2. 7.6.1.3.2 N[7:0] and N[10:8]
        4. 7.6.1.4  Register R1
          1. 7.6.1.4.1 NUM[21:12]
          2. 7.6.1.4.2 N[10:8] -- 3 MSB Bits for the N Counter
          3. 7.6.1.4.3 ICP[3:0] -- Charge Pump Current
        5. 7.6.1.5  Register R2
          1. 7.6.1.5.1 R[5:0] -- R Counter Value
          2. 7.6.1.5.2 DEN[21:12] and DEN[11:0]-- Fractional Denominator
        6. 7.6.1.6  Register R3
          1. 7.6.1.6.1 DEN[21:12] -- Extension for the Fractional Denominator
          2. 7.6.1.6.2 FoLD[3:0] -- Multiplexed Output for Ftest/LD Pin
          3. 7.6.1.6.3 ORDER -- Order of Delta-Sigma Modulator
          4. 7.6.1.6.4 DITHER -- Dithering
          5. 7.6.1.6.5 FDM -- Fractional Denominator Mode
          6. 7.6.1.6.6 DIV2
        7. 7.6.1.7  Register R4
          1. 7.6.1.7.1 TOC[13:0] -- Time-Out Counter for FastLock
          2. 7.6.1.7.2 ICPFL[3:0] -- Charge Pump Current for Fastlock
        8. 7.6.1.8  Register R5
          1. 7.6.1.8.1 EN_PLL -- Enable Bit for PLL
          2. 7.6.1.8.2 EN_VCO -- Enable Bit for the VCO
          3. 7.6.1.8.3 EN_OSC -- Enable Bit for the Oscillator Inverter
          4. 7.6.1.8.4 EN_VCOLDO -- Enable Bit for the VCO LDO
          5. 7.6.1.8.5 EN_PLLLDO1 -- Enable Bit for the PLL LDO 1
          6. 7.6.1.8.6 EN_PLLLDO2 -- Enable Bit for the PLL LDO 2
          7. 7.6.1.8.7 EN_DIGLDO -- Enable Bit for the digital LDO
          8. 7.6.1.8.8 REG_RST -- Resets All Registers to Default Settings
        9. 7.6.1.9  Register R6
          1. 7.6.1.9.1 C3_C4_ADJ[2:0] -- Value FOR C3 and C4 In The Internal Loop Filter
          2. 7.6.1.9.2 R3_ADJ_FL[1:0] -- Value for Internal Loop Filter Resistor R3 During Fastlock
          3. 7.6.1.9.3 R3_ADJ[1:0] -- Value for Internal Loop Filter Resistor R3
          4. 7.6.1.9.4 R4_ADJ_FL[1:0] -- Value for Internal Loop Filter Resistor R4 During Fastlock
          5. 7.6.1.9.5 R4_ADJ[1:0] -- Value for Internal Loop Filter Resistor R4
          6. 7.6.1.9.6 EN_LPFLTR-- Enable for Partially Integrated Internal Loop Filter
          7. 7.6.1.9.7 VCO_ACI_SEL
          8. 7.6.1.9.8 XTLSEL[2:0] -- OSCin Select
        10. 7.6.1.10 Register R7
          1. 7.6.1.10.1 XTLDIV[1:0] -- Division Ratio for the OSCin Frequency
          2. 7.6.1.10.2 XTLMAN[11:0] -- Manual OSCin Mode
        11. 7.6.1.11 Register R8
          1. 7.6.1.11.1 XTLMAN2 -- Manual Crystal Mode Second Adjustment
          2. 7.6.1.11.2 LOCKMODE -- Frequency Calibration Mode
        12. 7.6.1.12 Register R9
        13. 7.6.1.13 Register R12
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Typical Connection Diagram
        1. 10.1.1.1 VccDIG, VccVCO, VccBUF, and VccPLL
        2. 10.1.1.2 VregDIG
        3. 10.1.1.3 VrefVCO
        4. 10.1.1.4 VregVCO
        5. 10.1.1.5 VregPLL1VregPLL2
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
VCC
(VccDIG, VccVCO, VccBUF, VccPLL) 		Power Supply Voltage –0.3 3.5 V
All other pins
(Except Ground)		 Power Supply Voltage –0.3 3.0 V
TL Lead Temperature (solder 4 sec.) 260 °C
TJ Junction Temperature 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Power Supply Voltage
(VccDig, VccVCO, VccBUF)		 2.8 3.0 3.2 V
Vi Serial Interface and Power Control Voltage 0 2.75 V
TA Ambient Temperature(1) –40 85 °C
(1) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency calibration routine. This implies that the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of –40°C ≤ TA ≤ 85°C without violating specifications.

6.4 Thermal Information

THERMAL METRIC(1) LMX2531 LMX2531 UNIT
NJH0036D NJG0036A
36 PINS 36 PINS
RθJA Junction-to-ambient thermal resistance 35.5 35.5 °C/W
ψJB Junction-to-board characterization parameter 9.1 9.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

(VCC = 3.0 V, –40°C ≤ TA ≤ 85 °C; except as specified.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
ICC Power Supply Current Power Supply Current Divider Disabled LMX2531LQ2265E/
2570E		 38 44 mA
LMX2531LQ2820E/
3010E		 38 46
All Other Options 34 41
Divider Enabled LMX2531LQ2265E/
2570E		 41 49
LMX2531LQ2820E/
3010E		 44 52
All Other Options 37 46
ICCPD Power Down Current CE = 0 V, Part Initialized 7 µA
OSCILLATOR
IIHOSC Oscillator Input High Current VIH = 2.75 V 100 µA
IILOSC Oscillator Input Low Current VIL = 0 –100 µA
fOSCin Frequency Range See(1) 5 80 MHz
vOSCin Oscillator Sensitivity 0.5 2.0 Vpp
PLL
fPD Phase Detector Frequency 32 MHz
ICPout Charge Pump
Output Current Magnitude		 ICP = 0 90 µA
ICP = 1 180 µA
ICP = 3 360 µA
ICP = 15 1440 µA
ICPoutTRI CP TRI-STATE Current 0.4 V < VCPout < 2.0 V 2 10 nA
ICPoutMM Charge Pump
Sink vs Source Mismatch		 VCPout = 1.2 V
TA = 25°C		 2% 8%
ICPoutV Charge Pump
Current vs CP Voltage Variation		 0.4 V < VCPout < 2.0 V
TA = 25°C		 4%
ICPoutT CP Current vs Temperature Variation VCPout = 1.2 V 8%
LN(f) Normalized PLL 1/f Noise
LNPLL_flicker(10 kHz)
See(2)		 ICP = 1X Charge Pump Gain –94 dBc/Hz
ICP = 16X Charge Pump Gain –104
Normalized PLL Noise Floor
LNPLL_flat
See(3)		 ICP = 1X Charge Pump Gain –202 dBc/Hz
ICP = 16X Charge Pump Gain –212
VCO FREQUENCIES
fFout Operating Frequency Range
(All options have a frequency divider, this applies before the divider. The frequency after the divider is half of what is shown)		 LMX2531LQ1146E 1106 1184 MHz
LMX2531LQ1226E 1184 1268
LMX2531LQ1312E 1268 1360
LMX2531LQ1415E 1360 1470
LMX2531LQ1500E 1499 1510
LMX2531LQ1515E 1450 1580
LMX2531LQ1570E 1530 1636
LMX2531LQ1650E 1590 1700
LMX2531LQ1700E 1662 1770
LMX2531LQ1742 1760 1866
LMX2531LQ1778E 1726 1840
LMX2531LQ1910E 1834 2028
LMX2531LQ2080E 1904 2274
LMX2531LQ2265E 2178 2400
LMX2531LQ2570E 2336 2790
LMX2531LQ2820E 2710 2925
LMX2531LQ3010E 2910 3132
OTHER VCO SPECIFICATIONS
ΔTCL Maximum Allowable Temperature Drift for Continuous Lock
See(5)		 LMX2531LQ1742 65 °C
LMX2531LQ1500E/1570E/1650E/
1146E/1226/1312E/1415E/1515E		 90
LMX2531LQ1700E/1778E/1910E/
2080E/2265E/2570E/2820E/3010E		 125
pFout Output Power to a 50-Ω Load
(Applies across entire tuning range.)		 Divider Disabled LMX2531LQ1146E 1 4.0 7 dBm
LMX2531LQ1226E 1 3.5 7
LMX2531LQ1312E 1 3.5 7
LMX2531LQ1415E 0 3.0 6
LMX2531LQ1500E 1 3.5 7.0
LMX2531LQ1515E –1 2.5 5
LMX2531LQ1570E 2 4.5 8
LMX2531LQ1650E 2 4.5 8
LMX2531LQ1700E 1 3.5 7
LMX2531LQ1742 1 3.5 7
LMX2531LQ1778E 1 3.5 7
LMX2531LQ1910E 1 3.5 7
LMX2531LQ2080E 1 3.5 7
LMX2531LQ2265E 1 3.5 7
LMX2531LQ2570E 0 3.0 6
LMX2531LQ2820E –0.5 2.5 5.5
LMX2531LQ3010E –1.5 1.5 4.5
Divider Enabled LMX2531LQ1146E –1 2.0 5 dBm
LMX2531LQ1226E –1 2.0 5
LMX2531LQ1312E –1 1.5 4
LMX2531LQ1415E –2 0.5 3
LMX2531LQ1500E 1 3.0 6.0
LMX2531LQ1515E –2 0.5 3
LMX2531LQ1570E 1 3.0 6
LMX2531LQ1650E 1 3.0 6
LMX2531LQ1700E 1 3.0 6
LMX2531LQ1742 1 3.0 6
LMX2531LQ1778E 1 3.0 6
LMX2531LQ1910E 1 3.0 6
LMX2531LQ2080E 0 2.5 5
LMX2531LQ2265E 0 2.5 5
LMX2531LQ2570E –1 1.5 4
LMX2531LQ2820E –2.5 0 2.5
LMX2531LQ3010E –3 –0.5 2
KVtune Fine Tuning Sensitivity
(When a range is displayed in the typical column, indicates the lower sensitivity is typical at the lower end of the tuning range, and the higher tuning sensitivity is typical at the higher end of the tuning range.) 		LMX2531LQ1146E 2.5 — 5.5 MHz/V
LMX2531LQ1226E 3 — 6
LMX2531LQ1312E 3 — 6
LMX2531LQ1415E 3.5 — 6.5
LMX2531LQ1500E 4 — 7
LMX2531LQ1515E 4 — 7
LMX2531LQ1570E 4 — 7
LMX2531LQ1650E 4 — 7
LMX2531LQ1700E 6 — 10
LMX2531LQ1742 4 — 7
LMX2531LQ1778E 6 — 10
LMX2531LQ1910E 8 — 14
LMX2531LQ2080E 9 — 20
LMX2531LQ2265E 10 — 16
LMX2531LQ2570E 10 — 23
LMX2531LQ2820E 12 — 28
LMX2531LQ3010E 13 — 29
HSFout Harmonic Suppression
(Applies Across Entire Tuning Range)		 Second Harmonic
50 Ω Load 		Divider Disabled LMX2531LQ1146E
/1226E/1312E
/1415E/1515E		 –35 –25 dBc
LMX2531LQ2820E
/3010E		 –40
All Other Options –30 –25
Divider Enabled LMX2531LQ1146E
/1226E/1312E
/1415E/1515E		 –30 –20
LMX2531LQ2820E
/3010E		 –30 –15
All Other Options –20 –15
Third Harmonic
50 Ω Load		 Divider Disabled LMX2531LQ1146E
/1226E/1312E		 –35 –30
LMX2531LQ2820E
/3010E		 –50
All Other Options –40 –35
Divider Enabled LMX2531LQ1146E
/1226E/1312E
/1570E/1650E		 –20 –15
LMX2531LQ2820E
/3010E		 –40 –20
All Other Options –25 –20
PUSHFout Frequency Pushing Creg = 0.1 µF, VDD ± 100 mV, Open Loop 300 kHz/V
PULLFout Frequency Pulling VSWR = 2:1, Open Loop ±600 kHz
ZFout Output Impedance 50 Ω
VCO PHASE NOISE (4)
L(f)Fout Phase Noise
(LMX2531LQ1146E)		 fFout = 1146 MHz
DIV2 = 0		 10-kHz Offset –96 dBc/Hz
100-kHz Offset –121
1-MHz Offset –142
5-MHz Offset –156
fFout = 573 MHz
DIV2 = 1		 10-kHz Offset –101
100-kHz Offset –126
1-MHz Offset –147
5-MHz Offset –156
L(f)Fout Phase Noise
(LMX2531LQ1226E)		 fFout = 1226 MHz
DIV2 = 0		 10-kHz Offset –95 dBc/Hz
100-kHz Offset –121
1-MHz Offset –142
5-MHz Offset –155
fFout = 613 MHz
DIV2 = 1		 10-kHz Offset –101
100-kHz Offset –126
1-MHz Offset –147
5-MHz Offset –155
L(f)Fout Phase Noise
(LMX2531LQ1312E)		 fFout = 1314 MHz
DIV2 = 0		 10-kHz Offset –95 dBc/Hz
100-kHz Offset –121
1-MHz Offset –140
5-MHz Offset –154
fFout = 657 MHz
DIV2 = 1		 10-kHz Offset –101
100-kHz Offset –126
1-MHz Offset –146
5-MHz Offset –154
L(f)Fout Phase Noise
(LMX2531LQ1415E)		 fFout = 1415 MHz
DIV2 = 0		 10-kHz Offset –95 dBc/Hz
100-kHz Offset –121
1-MHz Offset –141
5-MHz Offset –154
fFout = 707.5 MHz
DIV2 = 1		 10-kHz Offset –100
100-kHz Offset –126
1-MHz Offset –146
5-MHz Offset –154
L(f)Fout Phase Noise
(LMX2531LQ1500E)		 fFout = 1500 MHz
DIV2 = 1		 10-kHz Offset –97 dBc/Hz
100-KHz Offset –120
1-MHz Offset –142
5-MHz Offset –155
fFout = 750 MHz
DIV2 = 1		 10-kHz Offset –103
100-kHz Offset –126
1-MHz Offset –131
5-MHz Offset –155
L(f)Fout Phase Noise
(LMX2531LQ1515E)		 fFout = 1515 MHz
DIV2 = 0		 10-kHz Offset –96 dBc/Hz
100-kHz Offset –122
1-MHz Offset –142
5-MHz Offset –153
fFout = 757.5 MHz
DIV2 = 1		 10-kHz Offset –99
100-kHz Offset –125
1-MHz Offset –145
5-MHz Offset –154
L(f)Fout Phase Noise
(LMX2531LQ1570E)		 fFout = 1583 MHz
DIV2 = 0		 10-kHz Offset –93 dBc/Hz
100-kHz Offset –118
1-MHz Offset –140
5-MHz Offset –154
fFout = 791.5 MHz
DIV2 = 1		 10-kHz Offset –99
100-kHz Offset –122
1-MHz Offset –144
5-MHz Offset –155
L(f)Fout Phase Noise
(LMX2531LQ1650E)		 fFout = 1645 MHz
DIV2 = 0		 10-kHz Offset –93 dBc/Hz
100-kHz Offset –118
1-MHz Offset –140
5-MHz Offset –154
fFout = 822.5 MHz
DIV2 = 1		 10-kHz Offset –99
100-kHz Offset –122
1-MHz Offset –144
5-MHz Offset –155
L(f)Fout Phase Noise
(LMX2531LQ1700E) 		fFout = 1716 MHz
DIV2 = 0		 10-kHz Offset –92 dBc/Hz
100-kHz Offset –117
1-MHz Offset –139
5-MHz Offset –153
fFout = 858 MHz
DIV2 = 1		 10-kHz Offset –98
100-kHz Offset –122
1-MHz Offset –144
5-MHz Offset –154
L(f)Fout Phase Noise
(LMX2531LQ1742)		 fFout= 1813 MHz
DIV2 = 0		 10-kHz Offset –92 dBc/Hz
100-kHz Offset –117
1-MHz Offset –140
5-MHz Offset –152
fFout = 906.5 MHz
DIV2 = 1		 10-kHz Offset –99
100-kHz Offset –122
1-MHz Offset –143
5-MHz Offset –152
L(f)Fout Phase Noise
(LMX2531LQ1778E)		 fFout = 1783 MHz
DIV2 = 0		 10-kHz Offset –92 dBc/Hz
100-kHz Offset –117
1-MHz Offset –139
5-MHz Offset –152
fFout = 891.5 MHz
DIV2 = 1		 10-kHz Offset –97
100-kHz Offset –122
1-MHz Offset –144
5-MHz Offset –154
L(f)Fout Phase Noise
(LMX2531LQ1910E)		 fFout = 1931 MHz
DIV2 = 0		 10-kHz Offset –89 dBc/Hz
100-kHz Offset –115
1-MHz Offset –138
5-MHz Offset –151
fFout = 965.5 MHz
DIV2 = 1		 10-kHz Offset –95
100-kHz Offset –121
1-MHz Offset –143
5-MHz Offset –155
L(f)Fout Phase Noise
(LMX2531LQ2080E)		 fFout = 2089 MHz
DIV2 = 0		 10-kHz Offset –87 dBc/Hz
100-kHz Offset –113
1-MHz Offset –136
5-MHz Offset –150
fFout = 1044.5 MHz
DIV2 = 1		 10-kHz Offset –93
100-kHz Offset –119
1-MHz Offset –142
5-MHz Offset –154
L(f)Fout Phase Noise
(LMX2531LQ2265E)		 fFout = 2264 MHz
DIV2 = 0		 10-kHz Offset –88 dBc/Hz
100-kHz Offset –113
1-MHz Offset –136
5-MHz Offset –150
fFout = 1132 MHz
DIV2 = 1		 10-kHz Offset –94
100-kHz Offset –118
1-MHz Offset –141
5-MHz Offset –154
L(f)Fout Phase Noise
(LMX2531LQ2570E)		 fFout = 2563 MHz
DIV2 = 0		 10-kHz Offset –86 dBc/Hz
100-kHz Offset –112
1-MHz Offset –135
5-MHz Offset –149
fFout = 1281.5 MHz
DIV2 = 1		 10-kHz Offset –91
100-kHz Offset –117
1-MHz Offset –139
5-MHz Offset –152
L(f)Fout Phase Noise
(LMX2531LQ2820E)		 fFout = 2818 MHz
DIV2 = 0		 10-kHz Offset –84 dBc/Hz
100-kHz Offset –111
1-MHz Offset –133
5-MHz Offset –148
fFout = 1409 MHz
DIV2 = 1		 10-kHz Offset –90
100-kHz Offset –117
1-MHz Offset –138
5-MHz Offset –150
L(f)Fout Phase Noise
(LMX2531LQ3010E)		 fFout = 3021 MHz
DIV2 = 0		 10-kHz Offset –83 dBc/Hz
100-kHz Offset –110
1-MHz Offset –132
5-MHz Offset –147
fFout = 1510.5 MHz
DIV2 = 1		 10-kHz Offset –88
100-kHz Offset –116
1-MHz Offset –137
5-MHz Offset –148
DIGITAL INTERFACE (DATA, CLK, LE, CE, Ftest/LD, FLout)
VIH High-Level Input Voltage 1.6 2.75 V
VIL Low-Level Input Voltage 0.4 V
IIH High-Level Input Current VIH = 1.75 –3.0 3.0 µA
IIL Low-Level Input Current VIL = 0 V –3.0 3.0 µA
VOH High-Level Output Voltage IOH = 500 µA 2.0 2.65 V
VOL Low-Level Output Voltage IOL = –500 µA 0.0 0.4 V
(1) There are program bits that need to be set based on the OSCin frequency. Refer to the following sections: XTLSEL[2:0] -- OSCin Select, XTLDIV[1:0] -- Division Ratio for the OSCin Frequency, XTLMAN[11:0] -- Manual OSCin Mode, XTLMAN2 -- Manual Crystal Mode Second Adjustment, and LOCKMODE -- Frequency Calibration Mode. Not all bit settings can be used for all frequency choices of OSCin. For instance, automatic modes described in XTLSEL[2:0] -- OSCin Select do not work below 8 MHz.
(2) One of the specifications for modeling PLL in-band phase noise is the PLL 1/f noise normalized to 1 GHz carrier frequency and 10 kHz offset, LPLL_flicker(10 kHz). From this normalized index of PLL 1/f noise, the PLL 1/f noise can be calculated for any carrier and offset frequency as: LNPLL_flicker(f) = LPLL_flicker(10 kHz) – 10 × log (10 kHz / f) + 20 × log ( Fout / 1 GHz ). Flicker noise can dominate at low offsets from the carrier and has a 10 dB/decade slope and improves with higher charge pump currents and at higher offset frequencies . To accurately measure LPLL_flicker(10 kHz) it is important to use a high phase detector frequency and a clean reference to make it such that this measurement is on the 10 dB/decade slope close to the carrier. LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat. In other words,LPLL(f) = 10 × log (10 (LNPLL_flat / 10 ) + 10(LNPLL_flicker (f) / 10 )
(3) A specification used for modeling PLL in-band phase noise floor is the Normalized PLL noise floor, LNPLL_flat, and is defined as: LNPLL_flat = L(f) – 20 × log (N) – 10 × log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector frequency of the synthesizer. LPLL_flat contributes to the total noise, L(f). To measure LPLL_flat the offset frequency must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and PLL flicker noise. LPLL_flat can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat. In other words, LPLL(f) = 10 × log (10 (LNPLL_flat / 10 ) + 10 (LNPLL_flicker (f) / 10 )
(4) The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The maximum limits apply only at center frequency and over temperature, assuming that the part is reloaded at each test frequency. Over frequency, the phase noise can vary 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies 1 to 2 dB, assuming the part is reloaded.
(5) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency calibration routine. This implies that the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of –40°C ≤TA≤ 85°C without violating specifications.

6.6 MICROWIRE Timing Requirements

See Figure 2 and Serial Data Timing Requirements.
MIN NOM MAX UNIT
tCS Data to Clock Set-Up Time 25 ns
tCH Data to Clock Hold Time 20 ns
tCWH Clock Pulse Width High 25 ns
tCWL Clock Pulse Width Low 25 ns
tES Clock to Enable Set-Up Time 25 ns
tCES Enable to Clock Set-Up Time 25 ns
tEWH Enable Pulse Width High 25 ns

6.7 Typical Performance Characteristics

20101106.gif
See Table 1.
Figure 1. OSCin Input Impedance