SNAS824B October 2021 – June 2022 LMX2571-EP
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | RESET | POWERDOWN | 0 | 0 | F1F2_INIT | 0 | F1F2_MODE | F1F2_SEL | 0 | 0 | 0 | 0 | 1 | FCAL_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-1h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
15-14 | R/W | 0h | Program 0h to this field. | |
13 | RESET | R/W | 0h | Resets all the registers to the default values. This bit is self-clearing. |
12 | POWERDOWN | R/W | 0h | Powers down the device. When the device comes out of the powered down state, either by resuming this bit to zero or by pulling back CE pin HIGH (if it was powered down by CE pin), it is required that register R0 with FCAL_EN = 1 be programmed again to re-calibrate the device. A 100-µs wait-time is recommended before programming R0. |
11 | R/W | 0h | Program this field to 0h. | |
10 | R/W | 0h |
Program this field to 0h. | |
9 | F1F2_INIT | R/W | 0h | Toggling this bit re-calibrates F1F2 if F1, F2 are
modified after calibration. This bit is not self-clear, so it is
required to clear the bit value after use. See Section 8.1.4 for details. |
8 | R/W | 0h |
Program this field to 0h. | |
7 | F1F2_MODE | R/W | 0h | Calibrates F1 and F2 during device initialization
(initial power on programming). Even if this bit
is not set, F1-F2 switching is still possible but
the first switching time will not be optimized
because either F1 or F2 will only be calibrated.
If F1-F2 switching is not required, set this bit
to zero. See Section 8.1.4 for details. |
6 | F1F2_SEL | R/W | 0h | Selects F1 or F2 configuration registers. |
5-1 | R/W | 1h | Program 1h to this field. | |
0 | FCAL_EN | R/W | 1h | Activates all kinds of calibrations, suggest keep it enabled all the time. If it is desired that the R0 register be programmed without activating this calibration, then this bit can be set to zero. |