SNAS824B October 2021 – June 2022 LMX2571-EP
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPBUFDIFF_TERM | 0 | 0 | 1 | 0 | 0 | 0 | FSK_I2S_FS_POL | FSK_I2S_CLK_POL | FSK_LEVEL | FSK_DEV_SEL | FSK_MODE_SEL0 | FSK_MODE_SEL1 | |||
R/W-0h | R/W-0h | R/W-2h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
15 | IPBUFDIFF_TERM | R/W | 0h | Enables independent 50 Ω input termination on the
OSCin Pin. |
14 | R/W | 0h |
Program 0h to this field. | |
13-11 | R/W | 2h |
Program 2h to this field. | |
10 | R/W | 0h |
Program 0h to this field. | |
9 | R/W | 0h | Program 0h to this field. | |
8 | FSK_I2S_FS_POL | R/W | 0h | Sets the polarity
of the I2S Frame Sync input in FSK I2S mode. |
7 | FSK_I2S_CLK_POL | R/W | 0h | Sets the polarity
of the I2S CLK input in FSK I2S mode. |
6-5 | FSK_LEVEL | R/W | 0h | Define the desired
FSK level in FSK PIN mode and FSK SPI mode. When this bit is
zero, FSK operation in these modes is disabled even if FSK_EN_Fx
= 1. |
4-2 | FSK_DEV_SEL | R/W | 0h | In FSK SPI mode,
these bits select one of the FSK deviations as defined in
registers R25-32 or R9-16. |
1 | FSK_MODE_SEL0 | R/W | 0h | FSK_MODE_SEL0 and
FSK_MODE_SEL1 define the FSK operation mode. FSK_MODE_SEL[1:0]
= |
0 | FSK_MODE_SEL1 | R/W | 0h | Same as above. |