SNAS824B October   2021  – June 2022 LMX2571-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Differences Between the LMX2571 and LMX2571-EP
      2. 7.3.2  Reference Oscillator Input
      3. 7.3.3  R-Dividers and Multiplier
      4. 7.3.4  PLL Phase Detector and Charge Pump
        1. 7.3.4.1 CPout Pin Charge Pump Current
        2. 7.3.4.2 Charge Pump Current When Using External VCO
      5. 7.3.5  PLL N-Divider and Fractional Circuitry
      6. 7.3.6  Partially Integrated Loop Filter
      7. 7.3.7  Low-Noise, Fully Integrated VCO
      8. 7.3.8  External VCO Support
      9. 7.3.9  Programmable RF Output Divider
      10. 7.3.10 Programmable RF Output Buffer
      11. 7.3.11 Integrated TX, RX Switch
      12. 7.3.12 Power Down
      13. 7.3.13 Lock Detect
      14. 7.3.14 FSK Modulation
      15. 7.3.15 FastLock
      16. 7.3.16 Register Readback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Duplex Mode
      3. 7.4.3 FSK Mode
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1  R60 Register (offset = 3Ch) [reset = 4000h]
      2. 7.6.2  R58 Register (offset = 3Ah) [reset = C00h]
      3. 7.6.3  R53 Register (offset = 35h) [reset = 2802h]
      4. 7.6.4  R47 Register (offset = 2Fh) [reset = 0h]
      5. 7.6.5  R46 Register (offset = 2Eh) [reset = 1Ah]
      6. 7.6.6  R42 Register (offset = 2Ah) [reset = 210h]
      7. 7.6.7  R41 Register (offset = 29h) [reset = 810h]
      8. 7.6.8  R40 Register (offset = 28h) [reset = 101Ch]
      9. 7.6.9  R39 Register (offset = 27h) [reset = 11F0h]
      10. 7.6.10 R35 Register (offset = 23h) [reset = 647h]
      11. 7.6.11 R34 Register (offset = 22h) [reset = 1000h]
      12. 7.6.12 R33 Register (offset = 21h) [reset = 0h]
      13. 7.6.13 R25 to R32 Register (offset = 19h to 20h) [reset = 0h]
      14. 7.6.14 R24 Register (offset = 18h) [reset = 10h]
      15. 7.6.15 R23 Register (offset = 17h) [reset = 10A4h]
      16. 7.6.16 R22 Register (offset = 16h) [reset = 8584h]
      17. 7.6.17 R21 Register (offset = 15h) [reset = 101h]
      18. 7.6.18 R20 Register (offset = 14h) [reset = 28h]
      19. 7.6.19 R19 Register (offset = 13h) [reset = 0h]
      20. 7.6.20 R18 Register (offset = 12h) [reset = 0h]
      21. 7.6.21 R17 Register (offset = 11h) [reset = 0h]
      22. 7.6.22 R9 to R16 Register (offset = 9h to 10h) [reset = 0h]
      23. 7.6.23 R8 Register (offset = 8h) [reset = 10h]
      24. 7.6.24 R7 Register (offset = 7h) [reset = 10A4h]
      25. 7.6.25 R6 Register (offset = 6h) [reset = 8584h]
      26. 7.6.26 R5 Register (offset = 5h) [reset = 101h]
      27. 7.6.27 R4 Register (offset = 4h) [reset = 28h]
      28. 7.6.28 R3 Register (offset = 3h) [reset = 0h]
      29. 7.6.29 R2 Register (offset = 2h) [reset = 0h]
      30. 7.6.30 R1 Register (offset = 1h) [reset = 0h]
      31. 7.6.31 R0 Register (offset = 0h) [reset = 3h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Direct Digital FSK Modulation
      2. 8.1.2  Frequency and Output Port Switching
      3. 8.1.3  OSCin Configuration
      4. 8.1.4  Register R0 F1F2_INIT, F1F2_MODE Usage
      5. 8.1.5  FastLock With External VCO
      6. 8.1.6  OSCin Slew Rate
      7. 8.1.7  RF Output Buffer Power Control
      8. 8.1.8  RF Output Buffer Type
      9. 8.1.9  MULT Multiplier
      10. 8.1.10 Integrated VCO
    2. 8.2 Typical Applications
      1. 8.2.1 Synthesizer Duplex Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Synthesizer Duplex Mode Application Curves
      2. 8.2.2 PLL Duplex Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 PLL Duplex Mode Application Curves
      3. 8.2.3 Synthesizer/PLL Duplex Mode
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Synthesizer/PLL Duplex Mode Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, VIO = VCC, –55 °C ≤ TA ≤ 125 °C, except as specified. Typical values are at VCC = VIO = 3.3 V, VCP = 3.3 V or 5 V in synthesizer mode, VCP = 5 V in PLL mode, TA = 25 °C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
ICC Synthesizer mode fOUT = 480 MHz, SE OSCIN Configuration A(1) 39 mA
Configuration B(2) 44
Configuration C(3) 46
Configuration D(4) 51
IPLL PLL mode Configuration E(5) 9
Configuration F(6) 15
Configuration G(7) 21
IPD Powerdown CE = 0 V or POWERDOWN = 1, VCC = 3.3 V, Push-pull output 0.9 mA
OSCIN REFERENCE INPUT
fOSCIN Input frequency 10 150 MHz
VOSCIN Input voltage(8) 0.8 3.3 V
REFERENCE INPUT PROGRAMMABLE MULTIPLIER
fMULTin MULT input frequency MULT > Pre-divider 10 30 MHz
fMULTout MULT output frequency 60 130
PLL
fPD Phase detector frequency 10 130 MHz
KPD Charge pump current(9) Programmable minimum value Internal charge pump 312.5 µA
5-V charge pump 625
Per programmable step Internal charge pump 312.5
5-V charge pump 625
Programmable maximum value Internal charge pump 7187.5
5-V charge pump 6875
PNPLL_1/f Normalized PLL 1/f noise(10) At maximum charge pump current Internal charge pump –124 dBc/Hz
5-V charge pump –120
PNPLL_FLAT Normalized PLL noise floor(10) Internal charge pump –231
5-V charge pump –226
fRFIN External VCO input frequency(11) EXTVCO_CHDIV = 1 100 2000 MHz
EXTVCO_CHDIV = 8, 10 100 1900
EXTVCO_CHDIV = 2, 3, 4, 5, 6, 7, 9 100 1400
PRFIN External VCO input power 0.1 GHz ≤ fRFIN < 1 GHz –10 dBm
1 GHz ≤ fRFIN ≤ 1.4 GHz –5
1.4 GHz < fRFIN ≤ 2 GHz 0
VCO
fVCO VCO frequency 4300 5376 MHz
KVCO VCO gain(12) fVCO = 4800 MHz 56 MHz/V
|ΔTCL| Allowable temperature drift(13) VCO not being recalibrated, –40 °C ≤ TA ≤ 125 °C 165 °C
tVCOCAL VCO calibration time fOSCIN = fPD = 100 MHz 140 µs
PNVCO Open loop VCO phase noise fOUT = 480 MHz 100 Hz offset –32.4 dBc/Hz
1 kHz offset –62.3
10 kHz offset –92.1
100 kHz offset –121.1
1 MHz offset –144.5
10 MHz offset –156.8
Outputs
fOUT RF output frequency Synthesizer mode 10 1344 MHz
PLL mode, RF output from buffer 10 1400
PTX, PRX RF output power fOUT = 480 MHz Power control bit = 6 0 dBm
H2RFout Second harmonic –25 dBc
DIGITAL FSK MODULATION
FSKLevel FSK level(14) FSK PIN mode 2 8
FSKBaud FSK baud rate(15) Loop bandwidth = 200 kHz 100 kSPs
FSKDev FSK deviation Configuration H(16) ±39 kHz
DIGITAL INTERFACE
VIH High-level input voltage 1.4 VCC V
VIL Low-Level input voltage 0.4 V
IIH High-level input current VIH = 1.75 V –25 25 µA
IIL Low-Level input current VIL = 0 V –25 25 µA
VOH High-level output voltage IOH = 500 μA 2 V
VOL Low-level input voltage IOL = –500 μA 0 0.4 V
(1) fOSCIN = 19.44 MHz, MULT = 1, Prescaler = 4, fPD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm
(2) fOSCIN = 19.44 MHz, MULT = 1, Prescaler = 2, fPD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm
(3) fOSCIN = 19.44 MHz, MULT = 5, Prescaler = 2, fPD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm
(4) fOSCIN = 19.44 MHz, MULT = 5, Prescaler = 2, fPD = 97.2 MHz, one RF output, output type = push pull, output power = –3 dBm
(5) fOSCIN = 19.44 MHz, MULT = 1, fPD = 19.44 MHz, output from VCO
(6) fOSCIN = 19.44 MHz, MULT = 1, fPD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm
(7) fOSCIN = 19.44 MHz, MULT = 1, fPD = 19.44 MHz, two RF outputs, output type = push pull, output power = –3 dBm
(8) See OSCIN Configuration for definition of OSCIN input voltage.
(9) This is referring to the total base charge pump current. In PLL mode, this is equal to EXTVCO_CP_IDN + EXTVCO_CP_IUP. In synthesizer mode, this is equal to CP_IDN + CP_IUP.
(10) Measured with a clean OSCIN signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an infinite loop bandwidth as:
PLL_Total = 10 * log[10(PLL_Flat / 10) + 10(PLL_Flicker / 10)]
PLL_Flat = PN1Hz + 20 * log(N) + 10 * log(fPD)
PLL_Flicker = PN10kHz – 10 * log(Offset / 10 kHz) + 20 * log(fOUT / 1 GHz)
(11) For external VCO frequencies above 1.4 GHz, there are restrictions on the output divider and register R70 needs to be programmed to 0x046110.
(12) The VCO gain changes as a function of the VCO core and frequency. See Integrated VCO for details.
(13) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial temperature and allowing this temperature to drift WITHOUT reprogramming the device, and still have the device stay in lock. This change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating temperatures of the device.
(14) The data showed here simply specifies the range of discrete FSK level that is supported in PIN mode. PIN mode supports 2-, 4- and 8-level of FSK modulation. If arbitrary level of FSK modulation is desired, use FSK SPI™ FAST mode or FSK I2S mode. See Direct Digital FSK Modulation for details.
(15) The baud rate is limited by the loop bandwidth of the PLL loop. As a general rule of thumb, it is desirable to have the loop bandwidth at least twice the baud rate.
(16) fPD = 100 MHz, DEN = 224, CHDIV1 = 5, CHDIV2 = 2, Prescaler = 2, FSK step value = 32716, 32819. The maximum achievable frequency deviation depends on the configuration, see Direct Digital FSK Modulation for details.