SNAS654 Data sheet

SNAS654A March 2015 – July 2016 LMX2571

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

NJK|36

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
V_CC	Power supply voltage	–0.3	3.6	V
V_IO	IO supply voltage	–0.3	3.6	V
V_IN	IO input voltage		V_CC + 0.3	V
V_CP	Charge pump supply voltage		5.25	V
T_J	Junction temperature		150	°C
T_STG	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_CC	Power supply voltage		3.15	3.45	V
V_IO	IO supply voltage			V_CC	V
V_CP	Charge pump supply voltage	PLL mode (external VCO)		5	V
V_CP	Charge pump supply voltage	Synthesizer mode (internal VCO)	V_CC	5	V
T_A	Ambient temperature		–40	85	°C
T_J	Junction temperature			125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMX2571	UNIT
		WQFN (NJK)
		36 PINS
R_θJA	Junction-to-ambient thermal resistance	32.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	14.5	°C/W
R_θJB	Junction-to-board thermal resistance	6.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	6.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.0	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

3.15 V ≤ V_CC ≤ 3.45 V, V_IO = V_CC, –40 °C ≤ T_A ≤ 85 °C, except as specified. Typical values are at V_CC = V_IO = 3.3 V, V_CP = 3.3 V or 5 V in synthesizer mode, V_CP = 5 V in PLL mode, T_A = 25 °C.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_CC	Total current in synthesizer mode (internal VCO)	f_OUT = 480 MHz SE OSCin	Configuration A⁽²⁾		39		mA
			Configuration B⁽³⁾		44
			Configuration C⁽⁴⁾		46
			Configuration D⁽⁵⁾		51
I_PLL	Total current in PLL mode (external VCO)		Configuration E⁽⁶⁾		9
			Configuration F⁽⁷⁾		15
			Configuration G⁽⁸⁾		21
I_CCPD	Power down current	CE = 0V or POWERDOWN bit = 1 V_CC = 3.3 V, Push-pull output			0.9
OSCIN REFERENCE INPUT
f_OSCin	OSCin frequency range	Single-ended or differential input		10		150	MHz
V_OSCin	OSCin input voltage⁽⁹⁾	Single-ended input		1.4		3.3	V
V_OSCin	OSCin input voltage⁽⁹⁾	Differential input		0.15		1.5	V
CRYSTAL REFERENCE INPUT
f_XTAL	Crystal frequency range	Fundamental model, ESR < 200 Ω		10		40	MHz
C_IN	OSCin input capacitance				1		pF
MULT
f_MULTin	MULT input frequency	MULT > Pre-divider Not supported with crystal reference input		10		30	MHz
f_MULTout	MULT output frequency			60		130	MHz
PLL
f_PD	Phase detector frequency					130	MHz
K_PD	Charge pump current⁽¹⁰⁾	Programmable minimum value	Internal charge pump		312.5		µA
		Programmable minimum value	5-V charge pump		625
		Per programmable step	Internal charge pump		312.5
		Per programmable step	5-V charge pump		625
		Programmable maximum value	Internal charge pump		7187.5
		Programmable maximum value	5-V charge pump		6875
PN_{PLL_1/f}	Normalized PLL 1/f noise⁽¹¹⁾	At maximum charge pump current	Internal charge pump		–124		dBc/Hz
PN_{PLL_1/f}	Normalized PLL 1/f noise⁽¹¹⁾		5-V charge pump		–120		dBc/Hz
PN_{PLL_Flat}	Normalized PLL noise floor⁽¹¹⁾		Internal charge pump		–231		dBc/Hz
PN_{PLL_Flat}	Normalized PLL noise floor⁽¹¹⁾		5-V charge pump		–226		dBc/Hz
f_RFin	External VCO input frequency⁽¹⁾	EXTVCO_CHDIV=1		100		2000	MHz
		EXTVCO_CHDIV=8,10		100		1900
		EXTVCO_CHDIV=2,3,4,5,6,7,9		100		1400
P_RFin	External VCO input power	0.1 GHz ≤ f_RFin < 1 GHz		–10			dBm
		1 GHz ≤ f_RFin ≤ 1.4 GHz		–5
		1.4 GHz < f_RFin ≤ 2 GHz		0
VCO
f_VCO	VCO frequency			4300		5376	MHz
K_VCO	VCO gain⁽¹²⁾	f_VCO = 4800 MHz			56		MHz/V
\| ΔT_CL \|	Allowable temperature drift⁽¹³⁾	VCO not being re-calibrated, –40 °C ≤ T_A ≤ 85 °C				125	°C
t_VCOCal	VCO calibration time	f_OSCin = f_PD = 100 MHz			140		µs
PN_VCO	Open loop VCO phase noise	f_OUT = 480 MHz	100 Hz offset		–32.4		dBc/Hz
			1 kHz offset		–62.3
			10 kHz offset		–92.1
			100 kHz offset		–121.1
			1 MHz offset		–144.5
			10 MHz offset		–156.8
RF OUTPUT
f_OUT	RF output frequency	Synthesizer mode		10		1344	MHz
f_OUT	RF output frequency	PLL mode, RF output from buffer		10		1400	MHz
P_TX, P_RX	RF output power	f_OUT = 480 MHz	Power control bit = 6		0		dBm
H2_RFout	Second harmonic	f_OUT = 480 MHz	Power control bit = 6		–25		dBc
DIGITAL FSK MODULATION
FSK_Level	FSK level⁽¹⁴⁾	FSK PIN mode		2		8
FSK_Baud	FSK baud rate⁽¹⁵⁾	Loop bandwidth = 200 kHz			100		kSPs
FSK_Dev	FSK deviation	Configuration H⁽¹⁶⁾			±39		kHz
DIGITAL INTERFACE
V_IH	High level input voltage			1.4		V_IO	V
V_IL	Low level input voltage					0.4	V
I_IH	High level input current	V_IH = 1.75 V		–25		25	µA
I_IL	Low level input current	V_IL= 0 V		–25		25	µA
V_OH	High level output voltage	I_OH = 500 µA		2			V
V_OL	Low level output voltage	I_OL = –500 µA			0	0.4	V

(1) For external VCO frequencies above 1.4 GHz, there are restrictions on the output divider and register R70 needs to be programmed to 0x046110.

(2) f_OSCin = 19.44 MHz, MULT = 1, Prescaler = 4, f_PD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(3) f_OSCin = 19.44 MHz, MULT = 1, Prescaler = 2, f_PD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(4) f_OSCin = 19.44 MHz, MULT = 5, Prescaler = 2, f_PD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(5) f_OSCin = 19.44 MHz, MULT = 5, Prescaler = 2, f_PD = 97.2 MHz, one RF output, output type = push pull, output power = –3 dBm

(6) f_OSCin = 19.44 MHz, MULT = 1, f_PD = 19.44 MHz, output from VCO

(7) f_OSCin = 19.44 MHz, MULT = 1, f_PD = 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(8) f_OSCin = 19.44 MHz, MULT = 1, f_PD = 19.44 MHz, two RF outputs, output type = push pull, output power = –3 dBm

(9) See OSCin Configuration for definition of OSCin input voltage.

(10) This is referring to the total base charge pump current. In PLL mode, this is equal to EXTVCO_CP_IDN + EXTVCO_CP_IUP. In synthesizer mode, this is equal to CP_IDN + CP_IUP. See Table 6, Table 7 and Table 8 for details.

(11) Measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an infinite loop bandwidth as:
PLL_Total = 10 * log[10^{(PLL_Flat / 10)} + 10^{(PLL_Flicker / 10)}]
PLL_Flat = PN1Hz + 20 * log(N) + 10 * log(f_PD)
PLL_Flicker = PN10kHz – 10 * log(Offset / 10 kHz) + 20 * log(f_OUT / 1 GHz)

(12) The VCO gain changes as a function of the VCO core and frequency. See Integrated VCO for details.

(13) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial temperature and allowing this temperature to drift WITHOUT reprogramming the device, and still have the device stay in lock. This change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating temperatures of the device.

(14) The data showed here simply specifies the range of discrete FSK level that is supported in PIN mode. PIN mode supports 2-, 4- and 8-level of FSK modulation. If arbitrary level of FSK modulation is desired, use FSK SPI™ FAST mode or FSK I2S mode. See Direct Digital FSK Modulation for details.

(15) The baud rate is limited by the loop bandwidth of the PLL loop. As a general rule of thumb, it is desirable to have the loop bandwidth at least twice the baud rate.

(16) f_PD = 100 MHz, DEN = 2²⁴, CHDIV1 = 5, CHDIV2 = 2, Prescaler = 2, FSK step value = 32716, 32819. The maximum achievable frequency deviation depends on the configuration, see Direct Digital FSK Modulation for details.

6.6 Timing Requirements

3.15 V ≤ V_CC ≤ 3.45 V, V_IO = V_CC, –40 °C ≤ T_A ≤ 85 °C, except as specified. Typical values are at V_CC = V_IO = 3.3 V, T_A = 25 °C.

			MIN	UNIT
MICROWIRE TIMING
t_ES	Clock to enable low time	See Figure 1	5	ns
t_CS	Data to clock setup time		2	ns
t_CH	Data to clock hold time		2	ns
t_CWH	Clock pulse width high		5	ns
t_CWL	Clock pulse width low		5	ns
t_CES	Enable to clock setup time		5	ns
t_EWH	Enable pulse width high		2	ns

Figure 1. MICROWIRE Timing Diagram

There are several other considerations for programming:

A slew rate of at least 30 V/µs is recommended for the CLK, DATA and LE. The same apply for other digital control signals such as FSK_D[0:2] and FSK_DV signals.
The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift register to an active register.
The LE pin may be held high after programming, causing the LMX2571 to ignore clock pulses.
When CLK or DATA lines are shared between devices, it is recommended to divide down the voltage to the CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity.
If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming.