8.3.1.1 Phase Noise Typical Performance Plot Explanations

Figure 2 shows 2700 MHz output and a 100 MHz phase detector frequency. The modeled noises (Flat, Flicker, and Total) are calculated from the normalized -229 dBc/Hz figure of merit and the -120.8 dBc/Hz normalized 1/f noise from the electrical table. After 200 kHz, the loop filter dynamics cause the noise to increase sharply.

Figure 3 shows the relative changes with the normalized PLL noise and figure of merit as a function of charge pump gain. The PLL phase noise changes as a function of the charge pump gain.

Figure 4 shows the phase noise for a filter optimized for spurs with a 20 MHz phase detector and running in fractional mode with strong dithering. Due to the narrower loop bandwidth, the impact of the VCO phase noise inside the loop bandwidth is in the 1 to 10 kHz region.

In Figure 5, the loop filter was optimized for RMS jitter. This was in fractional mode with a phase detector of 200 MHz and uses the First Order Modulator.

In Figure 6, the output divider noise floor only applies when the output divider is not bypassed and depends mainly on output frequency, not the actual divide value.

8.3.1.2 Other Typical Performance Plot Characteristics Explanations

Figure 7 shows a frequency change of 1880 MHz to 3760 MHz with Fosc = Fpd = 100 MHz. If the VCO3 is selected as the starting VCO with VCO_CAPCODE=127, digital calibration time is closer to 115 µs. If VCO4 is selected as the starting VCO with VCO_CAPCODE=15, the calibration time is greatly shortened to something of the order of 5 µs.

Figure 8 was measured with a board with very short traces. Only one of the differential outputs is routed.

In Figure 9, the output impedance is mainly determined by the pull-up component used at lower frequencies. For the resistor, it is 51 Ω up to about 2 GHz, where the impedance of the device starts to dominate. For the inductor it increases with frequency and then reaches a resonance frequency before coming down. These behaviors are specific to the pull-up component. These impedance plots match the conditions that were used to measure output power.

In Figure 12, the OSCin input sensitivity for a sine wave. The voltage has no impact and the temperature only has a slight impact. Enabling the doubler limits the performance

In Figure 13, For lower frequencies, the magnitude of the OSCin input impedance can be considered high relative to 50 Ω. At higher frequencies, it is not as high and a resistive pad may be better than a simple shunt 50 Ω resistor for matching.

Table 1. Approximate Change in VCO Phase Noise vs. Temperature and Temperature Drift in dB

8.3.5.1 Programmable Dithering Levels

If used appropriately, dithering may be used to reduce sub-fractional spurs, but if used inappropriately, it can actually create spurs and increase phase noise. Table 2 provides guidelines for the use of dithering based on the fractional denominator, after the fraction is reduced to lowest terms.

In general, dithering is likely to cause more harm than good for poorly randomized fractions like 1/2. There are situations when dithering does make sense and when it is used, it is recommended to adjust the PFD_DLY word accordingly to compensate for this.

8.3.5.2 Programmable Delta Sigma Modulator Order

The fractional modulator order is programmable, which gives the opportunity to better optimize phase noise and spurs. Theoretically, higher order modulators push out phase noise to farther offsets, as described in Table 3.

Figure 14 and Figure 15 give an idea of the theoretical impact of the delta sigma modulator order on the shaping of the phase noise and spurs. In terms of phase noise, this is what one would theoretically expect if strong dithering was used for a well-randomized fraction. Dithering can be set to different levels or even shut off and the noise can be eliminated. In terms of spurs, they can change based on fraction, but they will theoretically pushed out to higher phase detector frequencies. However, one must be aware that these are just THEORETICAL graphs and for offsets that on the order of less than 5% of the phase detector frequency, other factors can impact the noise and spurs. In Figure 14, the curves all cross at 1/6th of the phase detector frequency and that this transfer function peaks at half of the phase detector frequency, which is assumed to be well outside the loop bandwidth. Figure 15 shows the impact of the phase detector frequency on the modulator noise.

Figure 14. Theoretical Delta Sigma Noise Shaping for a 100 MHz Phase Detector Frequency

Figure 15. Theoretical Delta Sigma Noise Shaping for 3rd Order Modulator

Table 4. Impact of PFD_DLY, Modulator Order, and Phase Detector Frequency on Modulator Noise Floor

Table 5. Approximate (NOT Ensured) VCO Core Frequency Ranges

8.3.8.1 VCO Digital Calibration

When the frequency is changed, the digital VCO goes through the following VCO calibration:

1. Depending on the status of the VCO_SEL word, the starting VCO core is selected.
2. The algorithm starts counting at the default band in this core as determined by the VCO_CAPCODE value.
3. The VCO increments or decrements the CAPCODE based on the what the actual VCO output is compared to the target VCO output.
4. Repeat step 3 until either the VCO is locked or the VCO is at VCO_CAPCODE = 0 or 255
5. If not locked, then choose the next appropriate VCO if possible and return to step 3. If not possible, the calibration is terminated.

A good starting point is to set VCO_SEL = 2 for VCO 3 and set VCO_SEL_MODE = 1 to start at the selected core. If there is the potential of switching the VCO from a frequency above 3 GHz directly to a frequency below 2.2 GHz, VCO_SEL_MODE can not be set to 0. In this case, VCO_SEL_MODE can still be set to 1 to select a starting core, but the starting core specified by VCO_SEL can not be VCO 4.

The digital calibration time can be improved dramatically by giving the VCO guidance regarding which VCO core and which VCO_CAPCODE to start using. Even if the wrong VCO core is chosen, which could happen near the boundary of two cores, the calibration time is improved. For situations where the frequency change is small, the device can be programmed to automatically start at the last VCO core used. For applications where the frequency change is relatively small, the best VCO calibration time can often be achieved by setting the VCO_SEL_MODE to choose the last VCO core that was used.

Table 6. Output States of the RFoutA and RFoutB Pins

8.3.11.1 Choosing the Proper Pull-Up Component

The first decision is to whether to use a resistor or inductor for a pull up.

• The resistor pull-up involves placing a 50 Ω resistor to the power supply on each side, which makes the output impedance easy to match and close to 50 Ω. However, it is a higher current for the same output power, and the maximum possible output power is more limited. For this method, the OUTx_PWR setting should be kept about 30 or less (for a 3.3-V supply) to avoid saturation. The resistive pull-up is also sometimes more desirable when the output frequency is lower.
• The inductor pull-up involves placing an inductor to the power supply. This inductor should look like high impedance at the frequency of interest. This method offers higher output power for the same current and higher maximum output power. The output power is about 3 dB higher for the same OUTx_PWR setting than the resistor pull-up. Since the output impedance will be very high and poorly matched, it is recommended to either keep traces short or to AC couple this into a pad for better impedance matching.

If an output is partially used or unused:

• If the output is unused, then power it down in software. No external components are necessary.
• If only one side of the differential output is used, include the pull-up component and terminate the unused side, such that the impedance as seen by this pin looks similar to the impedance as seen by the used side.

8.3.11.2 Choosing the Best Setting for the RFoutA_PWR and RFoutB_PWR Words

Table 7 shows the impact of the RFoutX_PWR word on the output power and current RELATIVE to a setting of RFoutX_PWR = 15. The choice of pull-up component has an impact on the output power, but not much impact on the output current. The relative noise floor measurements are made without the VCO divider engaged.

For a resistive pull-up, a setting of 15 is optimal for noise floor and a setting if 30 is optimal for output power. Settings above 30 are generally not recommended for a resistive pull-up. For an inductor pull-up, a setting of 30 is optimal for noise floor and a setting of 45 is optimal for output power. These settings may vary a little based on output frequency, supply voltage, and loading of the output, but the above table gives a fairly close indication of what performance to expect.

Table 8. Normal Operation vs. Fastlock

Table 9. Fastlock Configuration

8.3.13.1 Vtune Lock Detect

This style of lock detect only works with the internal VCO. Whenever the tuning voltage goes below the threshold of about 0.5 V, or above the threshold of about 2.2 V, the internal VCO will become unlocked and the Vtune lock detect will indicate that the device is unlocked. For this reason, when the Vtune lock detect says the PLL is unlocked, one can be certain that it is unlocked.

8.3.13.2 Digital Lock Detect (DLD)

This lock detect works by comparing the phase error as presented to the phase detector. If the phase error plus the delay as specified by the PFD_DLY word outside the tolerance as specified by DLD_TOL, then this comparison would be considered to be an error, otherwise passing. At higher phase detector frequencies, it may be necessary to adjust the DLD_ERR_CNT and DLD_PASS_CNT. The DLD_ERR_CNT specifies how may errors are necessary to cause the circuit to consider the PLL to be unlocked. The DLD_PASS_CNT multiplied by 8 specifies how many passing comparisons are necessary to cause the PLL to be considered to be locked and also resets the count for the errors. The DLD_ERR_CNT and DLD_PASS_CNT values may be decreased to make the circuit more sensitive, but if lock detect is made too sensitive, chattering can occur and these values should be increased.

8.3.14.1 Uses of Readback

The LMX2581 allows any of its registers to be read back, which could be useful for the following applications below.

• Register Readback
  • By reading back the register values, it can be confirmed that the correct information was written. In addition to this, Register R6 has special diagnostic information that could potentially be useful for debugging problems.
• Part ID Readback
  • By reading back the part ID, this information may be used by whatever device is programming the LMX2581 to identify this device and know what programming information to send. In addition to this, the BUFEN and CE pins may be used to create 4 unique part ID values. Although these pins can impact the device, they may be overridden in software. It is not necessary to have the device programmed in order to do part ID Readback.

The procedure for doing this Readback is in the Serial Data Readback Timing section. Depending on the settings for the ID(R0[31]) and RDADDR (R6[8:5]), information a different bit stream will be returned as shown in Table 10.

8.3.14.2 Serial Timing for Readback

Readback is done through the the MUXout (or LD) pin with the same clock that is used to clock in the data.

• Choose either the MUXout (or LD) pin for reading back data and program the MUXOUT_SELECT (or LD_SELECT) to readback mode.
• Bring the LE pin from low to high to start the readback at the MSB.
• After the signal to the CLK pin goes high, the data will be ready at the readback pin 10 ns afterwards. It is recommended to read back the data on the falling edge of the clock. Technically, the first bit actually becomes ready after the rising edge of LE, but it still needs to be clocked out.
• The address being clocked out will all be 1's.

Because the CLK pin is both used to clock in data and clock out data, special care needs to be taken to ensure that erroneous data is not being clocked in during readback. There are two approaches to deal with this. The first approach is to actually send valid data during readback. For this approach, R6 is a recommended register and the approach is shown in Figure 18:

Figure 18. Timing for Readback

A second approach is to hold LE high during readback so that the clock pulses do not clock data into the part, but still function for readback purposes. Figure 19 demonstrates this method:

Figure 19. Timing for Readback, Holding LE High

8.3.15.1 Phase Detector Spur

The phase detector spur occurs at an offset from the carrier equal to the phase detector frequency, f_PD. To minimize this spur, considering using a smaller value for PFD_DLY, smaller value for CPG_BLEED, and a lower phase detector frequency. In some cases where the loop bandwidth is very wide relative to the phase detector frequency, some benefit might be gained from using a narrower loop bandwidth or adding poles to the loop filter, but otherwise the loop filter has minimal impact. Bypassing at the supply pins and board layout can also have an impact on this spur, especially at higher phase detector frequencies.

8.3.15.2 Fractional Spur - Integer Boundary Spur

This spur occurs at an offset equal to the difference between the VCO frequency and the closest integer channel for the VCO. For instance, if the phase detector frequency is 100 MHz and the VCO frequency was 2703 MHz, then the integer boundary spur would be at 3 MHz offset. This spur can be either PLL or VCO dominated. If it is PLL dominated, then the following table shows that decreasing the loop bandwidth and some of the programmable fractional words may impact this spur. If the spur is VCO dominated, then reducing the loop filter will not help, but rather reducing the phase detector and having a good slew rate and signal integrity at the OSCin pin will help. Regardless of whether it is PLL or VCO dominated, the VCO core does impact this spur.

It is common practice to benchmark a fractional PLL spurs by choosing a worst case VCO frequency and use this as a metric. However, one should be cautions that this is only a metric for the integer boundary spur. For instance, suppose that one was to compare two devices by using an 100 MHz phase detector frequency, tune the VCO to 2000.001 MHz, and measure the integer boundary spur at 1 kHz. If one part was to have better spurs at this frequency, this does not necessarily mean that the spurs would be better at a channel farther from an integer boundary, like 2025.001 MHz.

8.3.15.3 Fractional Spur - Primary Fractional Spurs

These spurs occur at multiples of f_PD / PLL_DEN and are not the integer boundary spur. For instance, if the phase detector frequency is 100 MHz and the fraction is 3/100, the primary fractional spurs would be at 1,2,4,5,6,...MHz. These are impacted by the loop filter bandwidth and modulator order. If a small frequency error is acceptable, then a larger equivalent fraction may improve these spurs. For instance, if the fraction is 53/200, expressing this as 530,000 / 2,000, 001. This larger unequivalent fraction pushes the fractional spur energy to much lower frequencies that hopefully is not so critical.

8.3.15.4 Fractional Spur - Sub-Fractional Spurs

These spurs appear at a fraction of f_PD / PLL_DEN and depend on modulator order. With the first order modulator, there are no sub-fractional spurs. The second order modulator can produce 1/2 sub-fractional spurs if the denominator is even. A third order modulator can produce sub-fractional spurs at 1/2,1/3, or 1/6 of the offset, depending if it is divisible by 2 or 3. For instance, if the phase detector frequency is 100 MHz and the fraction is 3/100, no sub-fractional spurs for a first order modulator or sub-fractional spurs at multiples of 1.5 MHz for a 2nd or 3rd order modulator would be expected.

Aside from strategically choosing the fractional denominator and using a lower order modulator, another tactic to eliminate these spurs is to use dithering and express the fraction in larger equivalent terms (that is, 1000000/4000000 instead of 1/4). If a small frequency error is acceptable, also consider a larger unequivalent fraction like (1000000,4000000). However, dithering can also add phase noise, so if dithering is used, this needs to be managed with the various levels it has and the PFD_DLY word to get the best possible performance.

8.3.15.5 Summary of Spurs and Mitigation Techniques

Table 12 gives a summary of the spurs discussed so far and techniques to mitigate them.

Table 13. LMX2581 Powerdown Modes

Table 14. Triggering Registers

8.6.1.1 Register R15

The programming of register R15 is only necessary when one wants to change the default value of VCO_CAPCODE for improving the VCO calibration time or use the VCO_CAP_MAN bit for diagnostic purposes.

8.6.1.2 Register R13

Register R13 gives access to words that are used for the digital lock detect circuitry.

8.6.1.3 Registers R10, R9, and R8

These registers control functions that are not disclosed to the user and the power on default values are not optimal. Therefore these registers need to be programmed to the values specified in the register map for proper operation.

8.6.1.4 Register R7

This register has words that control status pins, which would be LD, MUXout, and FLout

8.6.1.5 Register R6

8.6.1.6 Register R5

8.6.1.7 Register R4

8.6.1.8 Register R3

8.6.1.9 Register R2

8.6.1.10 Register R1

8.6.1.11 Register R0

Register R0 controls the frequency of the device. Also, unless disabled by setting NO_FCAL = 1, the action of writing to the R0 register triggers a frequency calibration for the internal VCO.