SNAS680E December   2015  – August 2022 LMX2582

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Distribution
      9. 7.3.9  Output Buffer
      10. 7.3.10 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2582 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Input Signal Path

The input signal path contains the components between the input (OSCin) buffer and the phase detector. The best PLL noise floor is achieved with a 200-MHz input signal for the highest dual-phase detector frequency. To address a wide range of applications, the input signal path contains the below components for flexible configuration before the phase detector. Each component can be bypassed. See Table 7-1 for usage boundaries if engaging a component.

  • OSCin doubler: This is low noise frequency doubler which can be used to multiply input frequencies by two. The doubler uses both the rising and falling edge of the input signal so the input signal must have 50% duty cycle if enabling the doubler. The best PLL noise floor is achieved with 200-MHz PFD, thus the doubler is useful if, for example, a very low-noise, 100-MHz input signal is available instead.
  • Pre-R divider: This is a frequency divider capable of very high frequency inputs. Use this to divide any input frequency up to 1400-MHz, and then the post-R divider if lower frequencies are needed.
  • Multiplier: This is a programmable, low noise multiplier. In combination with the Pre-R and Post-R dividers, the multiplier offers the flexibility to set a PFD away from frequencies that may create critical integer boundary spurs with the VCO and output frequencies. See the Section 8 section for an example. The user should not use the doubler while using the low noise programmable multiplier.
  • Post-R divider: Use this divider to divide down to frequencies below 5 MHz in extended PFD mode.

Table 7-1 Boundaries for Input Path Components
INPUTOUTPUT
LOW (MHz)HIGH (MHz)LOW (MHz)HIGH (MHz)
Input signal51400
OSCin doubler520010400
Pre-R divider1014005700
Multiplier4070180250
Post-R divider52500.25125
PFD0.25400