SNAS736C
June 2017 – April 2019
LMX2595
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Schematic
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Reference Oscillator Input
7.3.2
Reference Path
7.3.2.1
OSCin Doubler (OSC_2X)
7.3.2.2
Pre-R Divider (PLL_R_PRE)
7.3.2.3
Programmable Multiplier (MULT)
7.3.2.4
Post-R Divider (PLL_R)
7.3.2.5
State Machine Clock
7.3.3
PLL Phase Detector and Charge Pump
7.3.4
N-Divider and Fractional Circuitry
7.3.5
MUXout Pin
7.3.5.1
Lock Detect
7.3.5.2
Readback
7.3.6
VCO (Voltage-Controlled Oscillator)
7.3.6.1
VCO Calibration
7.3.6.2
Determining the VCO Gain
7.3.7
Channel Divider
7.3.8
VCO Doubler
7.3.9
Output Buffer
7.3.10
Power-Down Modes
7.3.11
Phase Synchronization
7.3.11.1
General Concept
7.3.11.2
Categories of Applications for SYNC
7.3.11.3
Procedure for Using SYNC
7.3.11.4
SYNC Input Pin
7.3.12
Phase Adjust
7.3.13
Fine Adjustments for Phase Adjust and Phase SYNC
7.3.14
Ramping Function
7.3.14.1
Manual Pin Ramping
7.3.14.1.1
Manual Pin Ramping Example
7.3.14.2
Automatic Ramping
7.3.14.2.1
Automatic Ramping Example (Triangle Wave)
7.3.15
SYSREF
7.3.15.1
Programmable Fields
7.3.15.2
Input and Output Pin Formats
7.3.15.2.1
Input Format for SYNC and SysRefReq Pins
7.3.15.2.2
SYSREF Output Format
7.3.15.3
Examples
7.3.15.4
SYSREF Procedure
7.3.16
SysRefReq Pin
7.4
Device Functional Modes
7.5
Programming
7.5.1
Recommended Initial Power-Up Sequence
7.5.2
Recommended Sequence for Changing Frequencies
7.5.3
General Programming Requirements
7.6
Register Maps
7.6.1
General Registers R0, R1, & R7
Table 25.
Field Descriptions
7.6.2
Input Path Registers
Table 26.
Field Descriptions
7.6.3
Charge Pump Registers (R13, R14)
Table 27.
Field Descriptions
7.6.4
VCO Calibration Registers
Table 28.
Field Descriptions
7.6.5
N Divider, MASH, and Output Registers
Table 29.
Field Descriptions
7.6.6
SYNC and SysRefReq Input Pin Register
Table 30.
Field Descriptions
7.6.7
Lock Detect Registers
Table 31.
Field Descriptions
7.6.8
MASH_RESET
Table 32.
Field Descriptions
7.6.9
SysREF Registers
Table 33.
Field Descriptions
7.6.10
CHANNEL Divider And VCO Doubler Registers
Table 34.
Field Descriptions
7.6.11
Ramping and Calibration Fields
Table 35.
Field Descriptions
7.6.12
Ramping Registers
7.6.12.1
Ramp Limits
Table 36.
Field Descriptions
7.6.12.2
Ramping Triggers, Burst Mode, and RAMP0_RST
Table 37.
Field Descriptions
7.6.12.3
Ramping Configuration
Table 38.
Field Descriptions
7.6.13
Readback Registers
Table 39.
Field Descriptions
8
Application and Implementation
8.1
Application Information
8.1.1
OSCin Configuration
8.1.2
OSCin Slew Rate
8.1.3
RF Output Buffer Power Control
8.1.4
RF Output Buffer Pullup
8.1.5
Performance Comparison Between 1572 (0x0624) and 3115 (0x0C2B) for Register DBLR_IBIAS_CTRL1 (R25[15:0])
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.1.2
Development Support
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
Community Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHA|40
MPQF135D
Thermal pad, mechanical data (Package|Pins)
RHA|40
QFND114P
Orderable Information
snas736c_oa
snas736c_pm
7
Detailed Description